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authorShelley Chen <shchen@google.com>2019-03-12 19:01:18 -0700
committerPatrick Georgi <pgeorgi@google.com>2019-03-14 11:28:31 +0000
commitc3de6203a75fb31ca7f4f222aad0560e39feffe0 (patch)
tree385895f691be7c127e92241310f9d08a474f1314 /src
parent38e27c3e92ac2588173bb547944c9b5aaa00536a (diff)
mb/google/hatch: fix RCompResistor[0] value
From doc#573387 CML System Memory DQ DQS Rcomp Mapping Information User Guide, RCompResistor[0] should be 121. BUG=b:122959294 BRANCH=None TEST=emerge coreboot and make sure boots up Change-Id: If69e7fb41e79d88d21b0e50fb65107a1686d696a Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31868 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src')
-rw-r--r--src/mainboard/google/hatch/variants/baseboard/memory.c4
1 files changed, 2 insertions, 2 deletions
diff --git a/src/mainboard/google/hatch/variants/baseboard/memory.c b/src/mainboard/google/hatch/variants/baseboard/memory.c
index 6ca98e4c7f..b6a66150fa 100644
--- a/src/mainboard/google/hatch/variants/baseboard/memory.c
+++ b/src/mainboard/google/hatch/variants/baseboard/memory.c
@@ -30,8 +30,8 @@ static const struct cnl_mb_cfg baseboard_memcfg = {
.dqs_map[DDR_CH0] = { 0, 1, 4, 5, 2, 3, 6, 7 },
.dqs_map[DDR_CH1] = { 0, 1, 4, 5, 2, 3, 6, 7 },
- /* Baseboard uses 120, 81 and 100 rcomp resistors */
- .rcomp_resistor = { 120, 81, 100 },
+ /* Baseboard uses 121, 81 and 100 rcomp resistors */
+ .rcomp_resistor = { 121, 81, 100 },
/* Baseboard Rcomp target values */
.rcomp_targets = { 100, 40, 20, 20, 26 },