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authorTimothy Pearson <tpearson@raptorengineeringinc.com>2016-03-29 20:37:36 -0500
committerTimothy Pearson <tpearson@raptorengineeringinc.com>2016-03-31 20:00:34 +0200
commitc094d9961144871c472698c41ce634e58abb6a32 (patch)
treed6abf49d3f8897fd45fc56134c0ecbfc8331f35b /src
parent3b55602b258e04b82dbb41f3332c5fb7f1b7bd81 (diff)
nb/amd/mct_ddr3: Disable MCE framework during DRAM training
On Family 15h processors, with certain RDIMMs, MCEs are generated as a normal part of DCT startup / DRAM training. Disable sync flood on parity or UC data error until ECC has been enabled. Change-Id: Ife54751ff127ffd59baaad35d3fea14ea01ef505 Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: https://review.coreboot.org/14186 Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src')
-rw-r--r--src/northbridge/amd/amdmct/mct_ddr3/mct_d.c13
-rw-r--r--src/northbridge/amd/amdmct/mct_ddr3/mct_d.h5
-rw-r--r--src/northbridge/amd/amdmct/mct_ddr3/mctecc_d.c28
3 files changed, 29 insertions, 17 deletions
diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c
index f144f8a4b4..6292f0b6ce 100644
--- a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c
+++ b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c
@@ -8019,14 +8019,27 @@ void mct_SetDramConfigHi_D(struct MCTStatStruc *pMCTstat,
printk(BIOS_DEBUG, "mct_SetDramConfigHi_D: DramConfigHi: %08x\n", DramConfigHi);
+ /* Prevent lockups on parity errors during initial DCT startup */
+ if (!pDCTstat->mca_config_backed_up) {
+ dword = Get_NB32(pDCTstat->dev_nbmisc, 0x44);
+ pDCTstat->sync_flood_on_dram_err = (dword >> 30) & 0x1;
+ pDCTstat->sync_flood_on_any_uc_err = (dword >> 21) & 0x1;
+ dword &= ~(0x1 << 30);
+ dword &= ~(0x1 << 21);
+ Set_NB32(pDCTstat->dev_nbmisc, 0x44, dword);
+ pDCTstat->mca_config_backed_up = 1;
+ }
+
/* Program the DRAM Configuration High register */
Set_NB32_DCT(dev, dct, 0x94, DramConfigHi);
if (is_fam15h()) {
/* Wait until F2x[1, 0]94[FreqChgInProg]=0. */
do {
+ printk(BIOS_DEBUG, "*");
dword = Get_NB32_DCT(pDCTstat->dev_dct, dct, 0x94);
} while (dword & (1 << FreqChgInProg));
+ printk(BIOS_DEBUG, "\n");
/* Program D18F2x9C_x0D0F_E006_dct[1:0][PllLockTime] = 0xf */
dword = Get_NB32_index_wait_DCT(pDCTstat->dev_dct, dct, index_reg, 0x0d0fe006);
diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.h b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.h
index fd35f9c2c9..6031239c06 100644
--- a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.h
+++ b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.h
@@ -580,6 +580,11 @@ struct DCTStatStruc { /* A per Node structure*/
uint8_t NbPstateThreshold;
uint8_t NbPstateHi;
+ /* MCA backup variables */
+ uint8_t mca_config_backed_up;
+ uint8_t sync_flood_on_dram_err;
+ uint8_t sync_flood_on_any_uc_err;
+
/* New for LB Support */
u8 NodePresent;
u32 dev_host;
diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mctecc_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mctecc_d.c
index be63149daf..2ebd09324b 100644
--- a/src/northbridge/amd/amdmct/mct_ddr3/mctecc_d.c
+++ b/src/northbridge/amd/amdmct/mct_ddr3/mctecc_d.c
@@ -85,8 +85,6 @@ u8 ECCInit_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstatA)
u16 nvbits;
uint32_t dword;
- uint8_t sync_flood_on_dram_err[MAX_NODES_SUPPORTED];
- uint8_t sync_flood_on_any_uc_err[MAX_NODES_SUPPORTED];
mctHookBeforeECC();
@@ -120,17 +118,6 @@ u8 ECCInit_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstatA)
pDCTstat = pDCTstatA + Node;
if (NodePresent_D(Node)) {
- dword = Get_NB32(pDCTstat->dev_nbmisc, 0x44);
- sync_flood_on_dram_err[Node] = (dword >> 30) & 0x1;
- sync_flood_on_any_uc_err[Node] = (dword >> 21) & 0x1;
- dword &= ~(0x1 << 30);
- dword &= ~(0x1 << 21);
- Set_NB32(pDCTstat->dev_nbmisc, 0x44, dword);
-
- /* Clear MC4 error status */
- pci_write_config32(pDCTstat->dev_nbmisc, 0x48, 0x0);
- pci_write_config32(pDCTstat->dev_nbmisc, 0x4c, 0x0);
-
/* Clear the RAM before enabling ECC to prevent MCE-related lockups */
DCTMemClr_Init_D(pMCTstat, pDCTstat);
DCTMemClr_Sync_D(pMCTstat, pDCTstat);
@@ -263,10 +250,17 @@ u8 ECCInit_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstatA)
pDCTstat = pDCTstatA + Node;
if (NodePresent_D(Node)) {
- dword = Get_NB32(pDCTstat->dev_nbmisc, 0x44);
- dword |= (sync_flood_on_dram_err[Node] & 0x1) << 30;
- dword |= (sync_flood_on_any_uc_err[Node] & 0x1) << 21;
- Set_NB32(pDCTstat->dev_nbmisc, 0x44, dword);
+ /* Clear MC4 error status */
+ pci_write_config32(pDCTstat->dev_nbmisc, 0x48, 0x0);
+ pci_write_config32(pDCTstat->dev_nbmisc, 0x4c, 0x0);
+
+ /* Restore previous MCA error handling settings */
+ if (pDCTstat->mca_config_backed_up) {
+ dword = Get_NB32(pDCTstat->dev_nbmisc, 0x44);
+ dword |= (pDCTstat->sync_flood_on_dram_err & 0x1) << 30;
+ dword |= (pDCTstat->sync_flood_on_any_uc_err & 0x1) << 21;
+ Set_NB32(pDCTstat->dev_nbmisc, 0x44, dword);
+ }
}
}