soc/amd: Specify memory types supported by each chip

This change disables support for memory types not used by each of the
chips.  This will in turn remove the files for those memory types from
the platform builds.

Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I8c7f47b43d8d4a89630fbd645a725e61d74bc2a5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68994
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>

6 files changed, 30 insertions, 0 deletions

diff --git a/src/soc/amd/cezanne/Kconfig b/src/soc/amd/cezanne/Kconfig
index 11f80766e8..1630df2e72 100644
--- a/src/soc/amd/cezanne/Kconfig
+++ b/src/soc/amd/cezanne/Kconfig
@@ -28,6 +28,9 @@ config SOC_SPECIFIC_OPTIONS
 	select HAVE_FSP_GOP
 	select HAVE_SMI_HANDLER
 	select IDT_IN_EVERY_STAGE
+	select NO_DDR5
+	select NO_DDR3
+	select NO_DDR2
 	select PARALLEL_MP_AP_WORK
 	select PLATFORM_USES_FSP2_0
 	select PROVIDES_ROM_SHARING
@@ -76,6 +79,8 @@ config SOC_SPECIFIC_OPTIONS
 	select SOC_AMD_COMMON_FSP_PCI
 	select SSE2
 	select UDK_2017_BINDING
+	select USE_DDR4
+	select USE_LPDDR4
 	select USE_FSP_NOTIFY_PHASE_POST_PCI_ENUM
 	select USE_FSP_NOTIFY_PHASE_READY_TO_BOOT
 	select USE_FSP_NOTIFY_PHASE_END_OF_FIRMWARE
diff --git a/src/soc/amd/glinda/Kconfig b/src/soc/amd/glinda/Kconfig
index c11ece9ca3..9e990992a8 100644
--- a/src/soc/amd/glinda/Kconfig
+++ b/src/soc/amd/glinda/Kconfig
@@ -31,6 +31,10 @@ config SOC_SPECIFIC_OPTIONS
 	select HAVE_FSP_GOP
 	select HAVE_SMI_HANDLER
 	select IDT_IN_EVERY_STAGE
+	select NO_DDR4
+	select NO_DDR3
+	select NO_DDR2
+	select NO_LPDDR4
 	select PARALLEL_MP_AP_WORK
 	select PLATFORM_USES_FSP2_0
 	select PROVIDES_ROM_SHARING
@@ -81,6 +85,7 @@ config SOC_SPECIFIC_OPTIONS
 	select SOC_AMD_COMMON_FSP_PCI			# TODO: Check if this is still correct
 	select SSE2
 	select UDK_2017_BINDING
+	select USE_DDR5
 	select USE_FSP_NOTIFY_PHASE_POST_PCI_ENUM
 	select USE_FSP_NOTIFY_PHASE_READY_TO_BOOT
 	select USE_FSP_NOTIFY_PHASE_END_OF_FIRMWARE
diff --git a/src/soc/amd/mendocino/Kconfig b/src/soc/amd/mendocino/Kconfig
index c03dbe22a3..3a1a29688e 100644
--- a/src/soc/amd/mendocino/Kconfig
+++ b/src/soc/amd/mendocino/Kconfig
@@ -41,6 +41,10 @@ config SOC_SPECIFIC_OPTIONS
 	select HAVE_FSP_GOP
 	select HAVE_SMI_HANDLER
 	select IDT_IN_EVERY_STAGE
+	select NO_DDR4
+	select NO_DDR3
+	select NO_DDR2
+	select NO_LPDDR4
 	select PARALLEL_MP_AP_WORK
 	select PLATFORM_USES_FSP2_0
 	select PROVIDES_ROM_SHARING
@@ -93,6 +97,7 @@ config SOC_SPECIFIC_OPTIONS
 	select SOC_AMD_COMMON_FSP_PCI		# TODO: Check if this is still correct
 	select SSE2
 	select UDK_2017_BINDING
+	select USE_DDR5
 	select USE_FSP_NOTIFY_PHASE_POST_PCI_ENUM
 	select USE_FSP_NOTIFY_PHASE_READY_TO_BOOT
 	select USE_FSP_NOTIFY_PHASE_END_OF_FIRMWARE
diff --git a/src/soc/amd/morgana/Kconfig b/src/soc/amd/morgana/Kconfig
index a1261c9771..814cb55c80 100644
--- a/src/soc/amd/morgana/Kconfig
+++ b/src/soc/amd/morgana/Kconfig
@@ -31,6 +31,10 @@ config SOC_SPECIFIC_OPTIONS
 	select HAVE_FSP_GOP
 	select HAVE_SMI_HANDLER
 	select IDT_IN_EVERY_STAGE
+	select NO_DDR4
+	select NO_DDR3
+	select NO_DDR2
+	select NO_LPDDR4
 	select PARALLEL_MP_AP_WORK
 	select PLATFORM_USES_FSP2_0
 	select PROVIDES_ROM_SHARING
@@ -81,6 +85,7 @@ config SOC_SPECIFIC_OPTIONS
 	select SOC_AMD_COMMON_FSP_PCI			# TODO: Check if this is still correct
 	select SSE2
 	select UDK_2017_BINDING
+	select USE_DDR5
 	select USE_FSP_NOTIFY_PHASE_POST_PCI_ENUM
 	select USE_FSP_NOTIFY_PHASE_READY_TO_BOOT
 	select USE_FSP_NOTIFY_PHASE_END_OF_FIRMWARE
diff --git a/src/soc/amd/picasso/Kconfig b/src/soc/amd/picasso/Kconfig
index f3b982d8ad..e8528268c9 100644
--- a/src/soc/amd/picasso/Kconfig
+++ b/src/soc/amd/picasso/Kconfig
@@ -27,6 +27,10 @@ config CPU_SPECIFIC_OPTIONS
 	select HAVE_EM100_SUPPORT
 	select HAVE_SMI_HANDLER
 	select IDT_IN_EVERY_STAGE
+	select NO_DDR5
+	select NO_DDR3
+	select NO_DDR2
+	select NO_LPDDR4
 	select PARALLEL_MP_AP_WORK
 	select PLATFORM_USES_FSP2_0
 	select PROVIDES_ROM_SHARING
@@ -69,6 +73,7 @@ config CPU_SPECIFIC_OPTIONS
 	select SOC_AMD_COMMON_FSP_DMI_TABLES
 	select SSE2
 	select UDK_2017_BINDING
+	select USE_DDR4
 	select USE_FSP_NOTIFY_PHASE_POST_PCI_ENUM
 	select USE_FSP_NOTIFY_PHASE_READY_TO_BOOT
 	select USE_FSP_NOTIFY_PHASE_END_OF_FIRMWARE
diff --git a/src/soc/amd/stoneyridge/Kconfig b/src/soc/amd/stoneyridge/Kconfig
index 53b986e68a..01800c1414 100644
--- a/src/soc/amd/stoneyridge/Kconfig
+++ b/src/soc/amd/stoneyridge/Kconfig
@@ -18,6 +18,10 @@ config CPU_SPECIFIC_OPTIONS
 	select HAVE_CF9_RESET
 	select HAVE_SMI_HANDLER
 	select HAVE_USBDEBUG_OPTIONS
+	select NO_DDR5
+	select NO_DDR3
+	select NO_DDR2
+	select NO_LPDDR4
 	select PARALLEL_MP_AP_WORK
 	select RTC
 	select SOC_AMD_PI
@@ -45,6 +49,7 @@ config CPU_SPECIFIC_OPTIONS
 	select SOC_AMD_COMMON_BLOCK_UART
 	select SSE2
 	select TSC_SYNC_LFENCE
+	select USE_DDR4
 	select X86_AMD_FIXED_MTRRS
 
 config AMD_APU_STONEYRIDGE