diff options
| author | Subrata Banik <subratabanik@google.com> | 2022-04-13 21:59:43 +0530 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2022-04-21 13:07:20 +0000 |
| commit | bca2f02ab7763f788db04c52673e7ba9d1a4b127 (patch) | |
| tree | 4e1bc9441871ed5bb4030fe558399a8ff2bf84ce /src | |
| parent | 5685cbb9587bc74bb46a8240bd0f99e1e54ef7cd (diff) | |
soc/intel/cmn/pch/lockdown: Perform additional SPI lock configuration
This patch performs additional SPI lock configuration as per Intel
Flash Security Specification.
BUG=b:211954778
TEST=Able to build google/brya and verified all flash security
recommendations are being met.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I922db8b46ac0d0523b91fc5aced88e38c8d8a560
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63627
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Diffstat (limited to 'src')
| -rw-r--r-- | src/soc/intel/common/pch/lockdown/lockdown.c | 9 |
1 files changed, 9 insertions, 0 deletions
diff --git a/src/soc/intel/common/pch/lockdown/lockdown.c b/src/soc/intel/common/pch/lockdown/lockdown.c index 739d13527b..8032b4ac3e 100644 --- a/src/soc/intel/common/pch/lockdown/lockdown.c +++ b/src/soc/intel/common/pch/lockdown/lockdown.c @@ -57,9 +57,18 @@ static void fast_spi_lockdown_cfg(int chipset_lockdown) /* Discrete Lock Flash PR registers */ fast_spi_pr_dlock(); + /* Check if SPI transaction is pending */ + fast_spi_cycle_in_progress(); + + /* Clear any outstanding status bits like AEL, FCERR, FDONE, SAF etc. */ + fast_spi_clear_outstanding_status(); + /* Lock FAST_SPIBAR */ fast_spi_lock_bar(); + /* Set Vendor Component Lock (VCL) */ + fast_spi_vscc0_lock(); + /* Set BIOS Interface Lock, BIOS Lock */ if (chipset_lockdown == CHIPSET_LOCKDOWN_COREBOOT) { /* BIOS Interface Lock */ |