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authorShaunak Saha <shaunak.saha@intel.com>2016-09-09 15:15:27 -0700
committerMartin Roth <martinroth@google.com>2016-09-15 01:20:06 +0200
commitb59991949580f59dbf0907881c7ea70729262e9a (patch)
tree546cde921f237ced83588e876da4f6ebcd550f85 /src
parent563de15b8a4aafad162352754975158222f8de6c (diff)
google/reef: Remove setting of GPIO_TIER1_SCI enable bit
This patch removes setting of gpio_tier1_sci_en from mainboard smihandler code. Gpio_tier1_sci enable bit is set from gpio.asl now. BUG=chrome-os-partner:56483 TEST=System resumes from S3 on lidopen, powerbutton and USB wake. Also from S0iX system is resuming for WIFI wake. Change-Id: I26fd3fd9fcc83c988bcff1bda4da7a2e3da98ce6 Signed-off-by: Shaunak Saha <shaunak.saha@intel.com> Reviewed-on: https://review.coreboot.org/16566 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Diffstat (limited to 'src')
-rw-r--r--src/mainboard/google/reef/smihandler.c3
1 files changed, 0 insertions, 3 deletions
diff --git a/src/mainboard/google/reef/smihandler.c b/src/mainboard/google/reef/smihandler.c
index dbf9162266..fe4f8c4de3 100644
--- a/src/mainboard/google/reef/smihandler.c
+++ b/src/mainboard/google/reef/smihandler.c
@@ -38,9 +38,6 @@ void mainboard_smi_sleep(u8 slp_typ)
pads = variant_sleep_gpio_table(&num);
gpio_configure_pads(pads, num);
- if (slp_typ == ACPI_S3)
- enable_gpe(GPIO_TIER_1_SCI);
-
if (IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC))
chromeec_smi_sleep(slp_typ, MAINBOARD_EC_S3_WAKE_EVENTS,
MAINBOARD_EC_S5_WAKE_EVENTS);