diff options
| author | Elyes HAOUAS <ehaouas@noos.fr> | 2019-04-28 17:52:10 +0200 |
|---|---|---|
| committer | Nico Huber <nico.h@gmx.de> | 2019-04-29 15:58:13 +0000 |
| commit | b559b3c78548c5b9089bed39c89ff72535f07814 (patch) | |
| tree | 35c2efffe07376ae5acd126eeb5b34cacd45f617 /src | |
| parent | cee06c458a915487cf6f5ee7053533f73084b603 (diff) | |
nb/x4x: Use system_reset() and full_reset()
Use already defined system_reset() and full_reset() functions.
Change-Id: I0a05f3ac5c5340a509024de2b444960f498c3e99
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32492
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Diffstat (limited to 'src')
| -rw-r--r-- | src/northbridge/intel/x4x/raminit.c | 10 |
1 files changed, 4 insertions, 6 deletions
diff --git a/src/northbridge/intel/x4x/raminit.c b/src/northbridge/intel/x4x/raminit.c index 4943428d0e..4d5bdce9ac 100644 --- a/src/northbridge/intel/x4x/raminit.c +++ b/src/northbridge/intel/x4x/raminit.c @@ -17,6 +17,7 @@ #include <arch/io.h> #include <device/pci_ops.h> #include <cbmem.h> +#include <cf9_reset.h> #include <console/console.h> #include <cpu/x86/cache.h> #include <cpu/x86/mtrr.h> @@ -654,13 +655,11 @@ void sdram_initialize(int boot_path, const u8 *spd_map) if (cache_not_found || (region_device_sz(&rdev) < sizeof(s))) { if (boot_path == BOOT_PATH_RESUME) { /* Failed S3 resume, reset to come up cleanly */ - outb(0x6, 0xcf9); - halt(); + system_reset(); } else if (boot_path == BOOT_PATH_WARM_RESET) { /* On warm reset some of dram calibrations fail and therefore requiring valid cached settings */ - outb(0xe, 0xcf9); - halt(); + full_reset(); } ctrl_cached = NULL; } else { @@ -728,8 +727,7 @@ void sdram_initialize(int boot_path, const u8 *spd_map) &s, sizeof(s)); if (s.boot_path == BOOT_PATH_RESUME && !cbmem_was_inited) { /* Failed S3 resume, reset to come up cleanly */ - outb(0x6, 0xcf9); - halt(); + system_reset(); } timestamp_add_now(TS_AFTER_INITRAM); |