diff options
| author | Peter Lemenkov <lemenkov@gmail.com> | 2019-12-09 11:42:56 +0100 |
|---|---|---|
| committer | Nico Huber <nico.h@gmx.de> | 2020-01-10 14:46:51 +0000 |
| commit | b48ca53091ffaf46aa11ed6937727d5de4a3c25b (patch) | |
| tree | b0ca3db80f002e28037971ce220b05161f0976e0 /src | |
| parent | 4b59fe402a6b76ada3792abf5dec95d144d1c9e9 (diff) | |
mb/lenovo/x1/devicetree: Rebalance against x220 one
Change-Id: Ib009c33d8393d4a76036941ac77965dc12e4ec3e
Signed-off-by: Peter Lemenkov <lemenkov@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37603
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src')
| -rw-r--r-- | src/mainboard/lenovo/x220/variants/x1/overridetree.cb | 22 |
1 files changed, 0 insertions, 22 deletions
diff --git a/src/mainboard/lenovo/x220/variants/x1/overridetree.cb b/src/mainboard/lenovo/x220/variants/x1/overridetree.cb index a08a12f588..68a70f08ce 100644 --- a/src/mainboard/lenovo/x220/variants/x1/overridetree.cb +++ b/src/mainboard/lenovo/x220/variants/x1/overridetree.cb @@ -15,31 +15,15 @@ chip northbridge/intel/sandybridge device domain 0 on subsystemid 0x17aa 0x21e8 inherit - device pci 00.0 on end # host bridge - device pci 02.0 on end # vga controller - chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH # Enable SATA ports 0 (HDD bay) & 2 (msata) & 3 (esatap) register "sata_port_map" = "0x1d" # X1 does not have ExpressCard slot register "pcie_hotplug_map" = "{ 0, 0, 0, 0, 0, 0, 0, 0 }" - device pci 1a.0 on end # USB2 EHCI #2 - device pci 1b.0 on end # High Definition Audio device pci 1c.0 off end # PCIe Port #1 - device pci 1c.1 on end # PCIe Port #2 (wlan) device pci 1c.2 off end # PCIe Port #3 device pci 1c.3 off end # PCIe Port #4 - device pci 1c.4 on - chip drivers/ricoh/rce822 # Ricoh cardreader - device pci 00.0 on end - end - end # PCIe Port #5 (SD) - device pci 1c.5 off end # PCIe Port #6 - device pci 1c.6 on end # PCIe Port #7 - device pci 1c.7 off end # PCIe Port #8 - device pci 1d.0 on end # USB2 EHCI #1 - device pci 1e.0 off end # PCI bridge device pci 1f.0 on #LPC bridge chip ec/lenovo/h8 register "config2" = "0xe0" @@ -50,14 +34,8 @@ chip northbridge/intel/sandybridge register "event5_enable" = "0x3c" register "evente_enable" = "0x3d" - - # BDC detection is broken on this board: - register "has_bdc_detection" = "0" end end # LPC bridge - device pci 1f.2 on end # SATA Controller 1 - device pci 1f.3 on end # SMBus - device pci 1f.6 on end # Thermal end end end |