diff options
| author | Rajneesh Bhardwaj <rajneesh.bhardwaj@intel.com> | 2017-06-18 10:45:09 +0530 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2017-06-27 20:46:40 +0000 |
| commit | b3f2c9ac5977ec4d4a0391a202f90a923d06895c (patch) | |
| tree | 336e5ede53495156324056cc2c7b6152e5c01d7d /src | |
| parent | 106e28582c2e4da73cbcf4b2349480ac87035604 (diff) | |
mb/google/soraka: Remove MPS IMVP8 workaround
Soraka uses MPS2949 IMVP8 controller and does not need the VR
workaroud similar to Eve.
BUG=None
TEST=Build & boot on soraka. Ensure IMVP8 controller goes to low power
mode in S3 and S0ix by measuring power.
Change-Id: Ib98bb709ecc9e362a5cef437e7319e41f398a73b
Signed-off-by: Rajneesh Bhardwaj <rajneesh.bhardwaj@intel.com>
Reviewed-on: https://review.coreboot.org/20255
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Diffstat (limited to 'src')
| -rw-r--r-- | src/mainboard/google/poppy/variants/soraka/devicetree.cb | 1 |
1 files changed, 0 insertions, 1 deletions
diff --git a/src/mainboard/google/poppy/variants/soraka/devicetree.cb b/src/mainboard/google/poppy/variants/soraka/devicetree.cb index 59f4684b93..2785131f43 100644 --- a/src/mainboard/google/poppy/variants/soraka/devicetree.cb +++ b/src/mainboard/google/poppy/variants/soraka/devicetree.cb @@ -57,7 +57,6 @@ chip soc/intel/skylake register "PmConfigSlpSusMinAssert" = "1" # 500ms register "PmConfigSlpAMinAssert" = "3" # 2s register "PmTimerDisabled" = "1" - register "SendVrMbxCmd" = "1" # IMVP8 workaround register "pirqa_routing" = "PCH_IRQ11" register "pirqb_routing" = "PCH_IRQ10" |