diff options
| author | Felix Held <felix-coreboot@felixheld.de> | 2021-05-25 20:53:19 +0200 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2021-05-27 15:39:30 +0000 |
| commit | ab1b606fd485f26563ec8fb4c84bf22c13b65a02 (patch) | |
| tree | c83532e515521c0d878fa1f80b7166f8f0716784 /src | |
| parent | a7c410b28602e337a85466429540663a7f3a219a (diff) | |
mb/amd/majolica: set PSPP policy to balanced
BUG=b:188793754
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I5fd0021170777c755ecb78d339aec05ff786710f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54932
Reviewed-by: Matt Papageorge <matthewpapa07@gmail.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src')
| -rw-r--r-- | src/mainboard/amd/majolica/devicetree.cb | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/src/mainboard/amd/majolica/devicetree.cb b/src/mainboard/amd/majolica/devicetree.cb index 0f540a151b..8f4fc9bfae 100644 --- a/src/mainboard/amd/majolica/devicetree.cb +++ b/src/mainboard/amd/majolica/devicetree.cb @@ -15,6 +15,8 @@ chip soc/amd/cezanne register "s0ix_enable" = "true" + register "pspp_policy" = "DXIO_PSPP_BALANCED" + device domain 0 on device ref gpp_gfx_bridge_0 on end # MXM device ref gpp_bridge_0 on end # NVMe |