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authorAngel Pons <th3fanbus@gmail.com>2021-08-29 11:10:13 +0200
committerFelix Held <felix-coreboot@felixheld.de>2021-09-06 19:10:35 +0000
commita6aaef77f4df30e17f135b115e5157f09eda2c3a (patch)
tree9fb7b3d9c0c801301a398eb94e561432bd28cf6e /src
parent7b615f8eebb491e1d81db149089075612bbde14e (diff)
mb/intel/kblrvp: Mark disabled SerialIO devices as `off`
Disable devicetree devices disabled in the `SerialIoDevMode` array. These devices get disabled by FSP-S, and coreboot doesn't see them. Change-Id: I8dbb45c96eae5188e5999df9a458f06f6b196adf Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57229 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-by: Nico Huber <nico.h@gmx.de>
Diffstat (limited to 'src')
-rw-r--r--src/mainboard/intel/kblrvp/variants/rvp11/overridetree.cb5
-rw-r--r--src/mainboard/intel/kblrvp/variants/rvp8/overridetree.cb5
2 files changed, 4 insertions, 6 deletions
diff --git a/src/mainboard/intel/kblrvp/variants/rvp11/overridetree.cb b/src/mainboard/intel/kblrvp/variants/rvp11/overridetree.cb
index 2301f7e346..df35e8a9f9 100644
--- a/src/mainboard/intel/kblrvp/variants/rvp11/overridetree.cb
+++ b/src/mainboard/intel/kblrvp/variants/rvp11/overridetree.cb
@@ -104,11 +104,10 @@ chip soc/intel/skylake
device domain 0 on
device pci 04.0 off end # SA thermal subsystem
+ device pci 15.2 off end # I2C #2
+ device pci 15.3 off end # I2C #3
device pci 17.0 on end # SATA
device pci 19.2 off end # I2C #4
- device pci 1e.1 on end # UART #1
- device pci 1e.2 on end # GSPI #0
- device pci 1e.3 on end # GSPI #1
device pci 1e.4 off end # eMMC
device pci 1e.6 off end # SDCard
device pci 1f.3 on end # Intel HDA
diff --git a/src/mainboard/intel/kblrvp/variants/rvp8/overridetree.cb b/src/mainboard/intel/kblrvp/variants/rvp8/overridetree.cb
index 4bb00dd6ce..869539647a 100644
--- a/src/mainboard/intel/kblrvp/variants/rvp8/overridetree.cb
+++ b/src/mainboard/intel/kblrvp/variants/rvp8/overridetree.cb
@@ -156,15 +156,14 @@ chip soc/intel/skylake
}"
device domain 0 on
+ device pci 15.2 off end # I2C #2
+ device pci 15.3 off end # I2C #3
device pci 17.0 on end # SATA
device pci 19.2 off end # I2C #4
device pci 1c.0 off end # PCI Express Port 1
device pci 1c.2 on end # PCI Express Port 3
device pci 1c.3 on end # PCI Express Port 4
device pci 1c.4 on end # PCI Express Port 5
- device pci 1e.1 on end # UART #1
- device pci 1e.2 on end # GSPI #0
- device pci 1e.3 on end # GSPI #1
device pci 1e.4 off end # eMMC
device pci 1e.6 off end # SDXC
device pci 1f.0 on