diff options
| author | Krishna Prasad Bhat <krishna.p.bhat.d@intel.com> | 2022-02-25 10:45:55 +0530 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2022-03-09 14:21:57 +0000 |
| commit | a67a92e3c081fe09fa75b23e8d2e2460ed5d16ae (patch) | |
| tree | e81c05d9f03c77ac4f3483815a25ec7aca4c50c6 /src | |
| parent | efdcb4634a6bea7cf900511f9b962c41d4e04fb0 (diff) | |
soc/intel/common: Add Kconfig to enable compression on ME_RW blobs
Add SOC_INTEL_CSE_LITE_COMPRESS_ME_RW Kconfig to enable compression on
ME_RW blobs. Select the Kconfig to add LZMA compressed ME_RW blobs to
ME_RW_A/B regions.
On ADL-N, this results in savings of ~665KB in each of ME_RW_A/B
regions.
FMAP REGION: ME_RW_A
Name Offset Type Size Comp
me_rw 0x0 raw 1275246 LZMA
(1957888 decompressed)
(empty) 0x1375c0 null 193056 none
FMAP REGION: ME_RW_B
Name Offset Type Size Comp
me_rw 0x0 raw 1275246 LZMA
(1957888 decompressed)
(empty) 0x1375c0 null 193056 none
Change-Id: I2e31c358b4969b077d65ce6369a877914d573aed
Signed-off-by: Krishna Prasad Bhat <krishna.p.bhat.d@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62358
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Reka Norman <rekanorman@chromium.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Diffstat (limited to 'src')
| -rw-r--r-- | src/soc/intel/common/block/cse/Kconfig | 7 | ||||
| -rw-r--r-- | src/soc/intel/common/block/cse/Makefile.inc | 3 |
2 files changed, 10 insertions, 0 deletions
diff --git a/src/soc/intel/common/block/cse/Kconfig b/src/soc/intel/common/block/cse/Kconfig index 164159c702..fb7548676e 100644 --- a/src/soc/intel/common/block/cse/Kconfig +++ b/src/soc/intel/common/block/cse/Kconfig @@ -150,6 +150,13 @@ config SOC_INTEL_CSE_NPHY_CBFS_FILE help CBFS path and file name for Intel CSE sub-partition NPHY binary +config SOC_INTEL_CSE_LITE_COMPRESS_ME_RW + bool + default n + depends on SOC_INTEL_CSE_LITE_SKU + help + Enable compression on Intel CSE CBFS RW blob + if STITCH_ME_BIN config CSE_COMPONENTS_PATH diff --git a/src/soc/intel/common/block/cse/Makefile.inc b/src/soc/intel/common/block/cse/Makefile.inc index 11a489178e..472ae9550c 100644 --- a/src/soc/intel/common/block/cse/Makefile.inc +++ b/src/soc/intel/common/block/cse/Makefile.inc @@ -85,6 +85,9 @@ cbfs-files-y += $(CSE_LITE_ME_RW) $(CSE_LITE_ME_RW)-file := $(CSE_RW_FILE) $(CSE_LITE_ME_RW)-name := $(CSE_LITE_ME_RW) $(CSE_LITE_ME_RW)-type := raw +ifeq ($(CONFIG_SOC_INTEL_CSE_LITE_COMPRESS_ME_RW),y) +$(CSE_LITE_ME_RW)-compression := LZMA +endif $(obj)/cse_rw.version: @echo '$(call strip_quotes,$(CONFIG_SOC_INTEL_CSE_RW_VERSION))' > $@ |