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authorSubrata Banik <subratabanik@google.com>2023-01-16 15:17:31 +0530
committerSubrata Banik <subratabanik@google.com>2023-01-18 11:50:50 +0000
commita5a357ca10f3c485f8269a5d8acac9c1851a0720 (patch)
treeb1e87b1556eed43674fb31975915d820b3977a19 /src
parentecf7db873c525e9bc0bd6d51ce757975aa0b82a6 (diff)
soc/intel/jasperlake: Fix incorrect `prev_sleep_state` issue
The patch fixes indication of incorrect `prev_sleep_state` on the next boot after global reset trigger. The existing code misses an important check about `if PCH doesn't set the WAK_STS` while checking power failure. As a result, every early warm/global reset is considered as power failure after looking into the PMC MMIO CON-A register alone (as ignoring the ACPI PM_CTRL.WAK_STS bit). As per the code comment this code logic is expected to check the power failure reason if PCH doesn't set the WAK_STS while waking from G3 state. TEST=Able to build and boot google/dedede. Without this patch: Observation: Resuming after a warm reset is considered as `prev_sleep_state 5` although the SLP_TYP is zero and WAK_STS bit is set. pm1_sts: 8100 pm1_en: 0000 pm1_cnt: 00000000 GEN_PMCON: d1215238 00002200 .... prev_sleep_state 5 With this patch: Observation: Resuming after a warm reset is considered as `prev_sleep_state 0`. It matches with the SLP_TYP is zero and WAK_STS bit is set. pm1_sts: 8100 pm1_en: 0000 pm1_cnt: 00000000 GEN_PMCON: d1215238 00002200 .... prev_sleep_state 0 Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: Id2c1f24a8fa54eea512b5bd3dd91423f9892687d Reviewed-on: https://review.coreboot.org/c/coreboot/+/71984 Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Diffstat (limited to 'src')
-rw-r--r--src/soc/intel/jasperlake/pmutil.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/soc/intel/jasperlake/pmutil.c b/src/soc/intel/jasperlake/pmutil.c
index b438e9db0e..744a2fb576 100644
--- a/src/soc/intel/jasperlake/pmutil.c
+++ b/src/soc/intel/jasperlake/pmutil.c
@@ -211,7 +211,7 @@ int soc_prev_sleep_state(const struct chipset_power_state *ps, int prev_sleep_st
* S5 because the PCH does not set the WAK_STS bit when waking
* from a true G3 state.
*/
- if (ps->gen_pmcon_a & (PWR_FLR | SUS_PWR_FLR))
+ if (!(ps->pm1_sts & WAK_STS) && (ps->gen_pmcon_a & (PWR_FLR | SUS_PWR_FLR)))
prev_sleep_state = ACPI_S5;
/*