diff options
| author | Aamir Bohra <aamir.bohra@intel.com> | 2019-08-16 12:20:01 +0530 |
|---|---|---|
| committer | Furquan Shaikh <furquan@google.com> | 2019-08-20 18:05:39 +0000 |
| commit | a4542990f4cd5d9a18e8b0846b54fcfe5cbd01e5 (patch) | |
| tree | c993bc47a63f6ce6ebd6accf7fb6f552ae9dab78 /src | |
| parent | 662c61d4497544d10c6b0d103ec7c27b5b084ee6 (diff) | |
mb/google/hatch: Skip SD card controller WP pin configuration from FSP
BUG=b:123907904
TEST=SD WP GPIO PAD retains coreboot configuration
and FSP ScsSdCardWpPinEnabled UPD is set to 0.
Change-Id: I30367cda09cc8c88abb649f70b4587889083f9af
Signed-off-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34901
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src')
| -rw-r--r-- | src/mainboard/google/hatch/variants/baseboard/devicetree.cb | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/src/mainboard/google/hatch/variants/baseboard/devicetree.cb b/src/mainboard/google/hatch/variants/baseboard/devicetree.cb index c87a8bcfe7..8b5fc1a403 100644 --- a/src/mainboard/google/hatch/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/hatch/variants/baseboard/devicetree.cb @@ -46,6 +46,8 @@ chip soc/intel/cannonlake register "tcc_offset" = "10" # TCC of 90C # Unlock GPIO pads register "PchUnlockGpioPads" = "1" + # SD card WP pin confguration + register "ScsSdCardWpPinEnabled" = "0" # NOTE: if any variant wants to override this value, use the same format # as register "common_soc_config.pch_thermal_trip" = "value", instead of |