soc/intel/alderlake: Wait for panel power cycle to complete

The Alder Lake PEIM graphics driver executed as part of the FSP does
not wait for the panel power cycle to complete before it initializes
communication with the display. It can result in AUX channel
communication time out and PEIM graphics driver failing to bring up
graphics.

If we have performed some graphics operation in romstage, it is
possible that a panel power cycle is still in progress. To prevent any
issue with the PEIM graphics driver it is preferable to ensure that
panel power cycle is complete.

This patch replaces commit ba2cef5b5493
("soc/intel/common/block/early_graphics: Introduce a 200 ms delay")
workaround patch.

BUG=b:264526798
BRANCH=firmware-brya-14505.B
TEST=Developer screen is visible in the recovery flow

Change-Id: Iadd6c9552b184f7d6ec8df9d0d392634864ba50b
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72419
Reviewed-by: Anil Kumar K <anil.kumar.k@intel.com>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>

3 files changed, 47 insertions, 17 deletions

diff --git a/src/drivers/intel/gma/i915_reg.h b/src/drivers/intel/gma/i915_reg.h
index f65c53290d..377f903292 100644
--- a/src/drivers/intel/gma/i915_reg.h
+++ b/src/drivers/intel/gma/i915_reg.h
@@ -3753,6 +3753,8 @@
 #define PIPEB_PP_DIVISOR        0x61310
 
 #define PCH_PP_STATUS		0xc7200
+#define  PANEL_POWER_CYCLE_ACTIVE	(1 << 27)
+
 #define PCH_PP_CONTROL		0xc7204
 #define  PANEL_UNLOCK_REGS	(0xabcd << 16)
 #define  PANEL_UNLOCK_MASK	(0xffff << 16)
diff --git a/src/soc/intel/alderlake/fsp_params.c b/src/soc/intel/alderlake/fsp_params.c
index 7c3ad912d9..4117c2215a 100644
--- a/src/soc/intel/alderlake/fsp_params.c
+++ b/src/soc/intel/alderlake/fsp_params.c
@@ -3,9 +3,12 @@
 #include <assert.h>
 #include <console/console.h>
 #include <cpu/intel/microcode.h>
+#include <delay.h>
 #include <device/device.h>
 #include <device/pci.h>
 #include <device/pci_ids.h>
+#include <device/pci_ops.h>
+#include <drivers/intel/gma/i915_reg.h>
 #include <fsp/api.h>
 #include <fsp/fsp_debug_event.h>
 #include <fsp/ppi/mp_service_ppi.h>
@@ -1205,6 +1208,46 @@ static void soc_silicon_init_params(FSP_S_CONFIG *s_cfg,
 		fill_fsps_params[i](s_cfg, config);
 }
 
+/*
+ * The Alder Lake PEIM graphics driver executed as part of the FSP does not wait
+ * for the panel power cycle to complete before it initializes communication
+ * with the display. It can result in AUX channel communication time out and
+ * PEIM graphics driver failing to bring up graphics.
+ *
+ * If we have performed some graphics operations in romstage, it is possible
+ * that a panel power cycle is still in progress. To prevent any issue with the
+ * PEIM graphics driver it is preferable to ensure that panel power cycle is
+ * complete.
+ *
+ * BUG:b:264526798
+ */
+static void wait_for_panel_power_cycle_done(const struct soc_intel_alderlake_config *config)
+{
+	const struct i915_gpu_panel_config *panel_cfg;
+	uint32_t bar0;
+	void *mmio;
+
+	if (!CONFIG(RUN_FSP_GOP))
+		return;
+
+	bar0 = pci_s_read_config32(SA_DEV_IGD, PCI_BASE_ADDRESS_0);
+	mmio = (void *)(bar0 & ~PCI_BASE_ADDRESS_MEM_ATTR_MASK);
+	if (!mmio)
+		return;
+
+	panel_cfg = &config->panel_cfg;
+	for (size_t i = 0;; i++) {
+		uint32_t status = read32(mmio + PCH_PP_STATUS);
+		if (!(status & PANEL_POWER_CYCLE_ACTIVE))
+			break;
+		if (i == panel_cfg->cycle_delay_ms) {
+			printk(BIOS_ERR, "Panel power cycle is still active.\n");
+			break;
+		}
+		mdelay(1);
+	}
+}
+
 /* UPD parameters to be initialized before SiliconInit */
 void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
 {
@@ -1214,6 +1257,8 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
 	config = config_of_soc();
 	soc_silicon_init_params(s_cfg, config);
 	mainboard_silicon_init_params(s_cfg);
+
+	wait_for_panel_power_cycle_done(config);
 }
 
 /*
diff --git a/src/soc/intel/common/block/graphics/early_graphics.c b/src/soc/intel/common/block/graphics/early_graphics.c
index 8157a4c284..81faede2fa 100644
--- a/src/soc/intel/common/block/graphics/early_graphics.c
+++ b/src/soc/intel/common/block/graphics/early_graphics.c
@@ -1,6 +1,5 @@
 /* SPDX-License-Identifier: GPL-2.0-or-later */
 
-#include <delay.h>
 #include <device/pci.h>
 #include <drivers/intel/gma/libgfxinit.h>
 #include <intelblocks/early_graphics.h>
@@ -44,20 +43,4 @@ void early_graphics_stop(void)
 		return;
 
 	gma_gfxstop();
-
-	/*
-	 * Temporary workaround
-	 *
-	 * It has been reported that the PEIM graphics driver may temporarily
-	 * fail communication with the display if the time between libgfxinit
-	 * turning off the displays and the PEIM driver initialization is too
-	 * short. 200 ms has been identified as a safe delay.
-	 *
-	 * An investigation is in progress to come up with a better and long
-	 * term solution.
-	 *
-	 * BUG:b:264526798
-	 */
-	if (CONFIG(RUN_FSP_GOP))
-		mdelay(200);
 }