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authorJan Samek <jan.samek@siemens.com>2022-12-01 14:52:51 +0100
committerMartin L Roth <gaumless@gmail.com>2022-12-17 20:39:44 +0000
commita1a8f58a0713dad8bc621daf180790504b897dda (patch)
tree0011a15913fdc835de5d1404ae28caeefdc41e20 /src
parenta2035cc4d08b0894121024376a8e06749c911dfb (diff)
mb/siemens/mc_ehl3/devicetree.cb: Adapt PCIe root port settings
Based upon hardware differences from mc_ehl2, disable RP7 and enable RP3 and RP5. Change-Id: Iecaa3098c3e4c9ce15254bb8bd1fe6da86d6e706 Signed-off-by: Jan Samek <jan.samek@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70689 Reviewed-by: Uwe Poeche <uwe.poeche@siemens.com> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src')
-rw-r--r--src/mainboard/siemens/mc_ehl/variants/mc_ehl3/devicetree.cb20
1 files changed, 12 insertions, 8 deletions
diff --git a/src/mainboard/siemens/mc_ehl/variants/mc_ehl3/devicetree.cb b/src/mainboard/siemens/mc_ehl/variants/mc_ehl3/devicetree.cb
index c922e9e988..7281a7fa45 100644
--- a/src/mainboard/siemens/mc_ehl/variants/mc_ehl3/devicetree.cb
+++ b/src/mainboard/siemens/mc_ehl/variants/mc_ehl3/devicetree.cb
@@ -43,14 +43,15 @@ chip soc/intel/elkhartlake
# PCIe root ports related UPDs
register "PcieRpEnable[1]" = "1"
- register "PcieRpEnable[6]" = "1"
+ register "PcieRpEnable[2]" = "1"
+ register "PcieRpEnable[4]" = "1"
register "PcieClkSrcUsage[0]" = "PCIE_CLK_NOTUSED"
register "PcieClkSrcUsage[1]" = "PCIE_CLK_FREE"
- register "PcieClkSrcUsage[2]" = "PCIE_CLK_NOTUSED"
+ register "PcieClkSrcUsage[2]" = "PCIE_CLK_FREE"
register "PcieClkSrcUsage[3]" = "PCIE_CLK_NOTUSED"
- register "PcieClkSrcUsage[4]" = "PCIE_CLK_FREE"
- register "PcieClkSrcUsage[5]" = "PCIE_CLK_NOTUSED"
+ register "PcieClkSrcUsage[4]" = "PCIE_CLK_NOTUSED"
+ register "PcieClkSrcUsage[5]" = "PCIE_CLK_FREE"
register "PcieClkSrcClkReq[0]" = "PCIE_CLK_NOTUSED"
register "PcieClkSrcClkReq[1]" = "PCIE_CLK_NOTUSED"
@@ -61,11 +62,13 @@ chip soc/intel/elkhartlake
# Disable all L1 substates for PCIe root ports
register "PcieRpL1Substates[1]" = "L1_SS_DISABLED"
- register "PcieRpL1Substates[6]" = "L1_SS_DISABLED"
+ register "PcieRpL1Substates[2]" = "L1_SS_DISABLED"
+ register "PcieRpL1Substates[4]" = "L1_SS_DISABLED"
# Disable LTR for all PCIe root ports
register "PcieRpLtrDisable[1]" = "true"
- register "PcieRpLtrDisable[6]" = "true"
+ register "PcieRpLtrDisable[2]" = "true"
+ register "PcieRpLtrDisable[4]" = "true"
# Storage (SDCARD/EMMC) related UPDs
register "ScsEmmcHs400Enabled" = "0"
@@ -178,8 +181,9 @@ chip soc/intel/elkhartlake
device pci 1a.0 on end # eMMC
device pci 1a.1 on end # SD
- device pci 1c.1 on end # RP2 (pcie0 single VC)
- device pci 1c.6 on end # RP7 (pcie3 multi VC)
+ device pci 1c.1 on end # RP2
+ device pci 1c.2 on end # RP3
+ device pci 1c.4 on end # RP5
device pci 1d.0 off end # Intel PSE IPC (local host to PSE)
device pci 1d.1 on # Intel PSE Time-Sensitive Networking GbE 0