diff options
| author | Subrata Banik <subratabanik@google.com> | 2022-01-31 23:30:55 +0530 |
|---|---|---|
| committer | Subrata Banik <subratabanik@google.com> | 2022-02-02 07:00:29 +0000 |
| commit | a0dd454115ad61821b171c400b2b5472f2f5b861 (patch) | |
| tree | d0f4495533113c9e4557cc84bf38296af5728525 /src | |
| parent | abac030662b8aff500299b96972b6063ea755ab9 (diff) | |
mb/google/brya: Lock PCH WP pin in brask and brya baseboards
This applies a configuration lock to the PCH write protect GPIO for
all brya and brask variants.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: Ia125c513c09ecbb1047100e72f8540369646988e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61501
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Diffstat (limited to 'src')
| -rw-r--r-- | src/mainboard/google/brya/variants/baseboard/brask/gpio.c | 2 | ||||
| -rw-r--r-- | src/mainboard/google/brya/variants/baseboard/brya/gpio.c | 3 |
2 files changed, 2 insertions, 3 deletions
diff --git a/src/mainboard/google/brya/variants/baseboard/brask/gpio.c b/src/mainboard/google/brya/variants/baseboard/brask/gpio.c index 22b2c702e3..203f6d9da4 100644 --- a/src/mainboard/google/brya/variants/baseboard/brask/gpio.c +++ b/src/mainboard/google/brya/variants/baseboard/brask/gpio.c @@ -189,7 +189,7 @@ static const struct pad_config gpio_table[] = { /* E14 : DDSP_HPDA ==> SOC_DP_HPD */ PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1), /* E15 : RSVD_TP ==> PCH_WP_OD */ - PAD_CFG_GPI_GPIO_DRIVER(GPP_E15, NONE, DEEP), + PAD_CFG_GPI_GPIO_DRIVER_LOCK(GPP_E15, NONE, LOCK_CONFIG), /* E16 : RSVD_TP ==> CLKREQ_8 */ PAD_NC(GPP_E16, NONE), /* E17 : THC0_SPI1_INT# ==> TP102 */ diff --git a/src/mainboard/google/brya/variants/baseboard/brya/gpio.c b/src/mainboard/google/brya/variants/baseboard/brya/gpio.c index fffbbc835c..7db7cd4048 100644 --- a/src/mainboard/google/brya/variants/baseboard/brya/gpio.c +++ b/src/mainboard/google/brya/variants/baseboard/brya/gpio.c @@ -188,7 +188,7 @@ static const struct pad_config gpio_table[] = { /* E14 : DDSP_HPDA ==> SOC_EDP_HPD */ PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1), /* E15 : RSVD_TP ==> PCH_WP_OD */ - PAD_CFG_GPI_GPIO_DRIVER(GPP_E15, NONE, DEEP), + PAD_CFG_GPI_GPIO_DRIVER_LOCK(GPP_E15, NONE, LOCK_CONFIG), /* E16 : RSVD_TP ==> WWAN_RST_L */ PAD_CFG_GPO(GPP_E16, 1, DEEP), /* E17 : THC0_SPI1_INT# ==> WWAN_CONFIG3 */ @@ -458,7 +458,6 @@ const struct pad_config *__weak variant_romstage_gpio_table(size_t *num) } static struct gpio_lock_config lockable_brya_gpios[] = { - { GPP_E15, GPIO_LOCK_CONFIG }, /* PCH_WP_OD */ { GPP_F11, GPIO_LOCK_CONFIG }, /* GSPI_PCH_CLK_FPMCU_R */ { GPP_F13, GPIO_LOCK_CONFIG }, /* GSPI_PCH_D1_FPMCU_D0 */ { GPP_F12, GPIO_LOCK_CONFIG }, /* GSPI_PCH_D0_FPMCU_D1_R */ |