diff options
| author | Bora Guvendik <bora.guvendik@intel.com> | 2023-05-15 14:28:44 -0700 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2023-05-26 17:57:12 +0000 |
| commit | 9f15dee56d7fbebe22cb15d55279f05c85a75832 (patch) | |
| tree | e30fe825dfcfec1d4795639fdf38ba9cc33cc145 /src | |
| parent | db17ebccee974ccf4830dfa2e19d29361478050f (diff) | |
soc/intel/meteorlake: Hook up SaGvFreq, SaGvGear upds
Hook the SaGvFreq, SaGvGear upds so that mainboard can change the
settings via devicetree. Meteor Lake supports 4 SaGv work points and it
can dynamically scale the work point based on memory bandwidth
utilization. Dynamic gearing technology allows the Memory Controller to
run at 1:1, 1:2 or 1:4 ratio of DRAM speed. The gear ratio is the ratio
of DRAM speed to Memory Controller Clock.
BUG=b:282164577
TEST=Verified the settings on google/rex using debug FSP logs.
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Change-Id: I37169880af4019675374594e90735b5d7d0873b8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75290
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src')
| -rw-r--r-- | src/soc/intel/meteorlake/chip.h | 11 | ||||
| -rw-r--r-- | src/soc/intel/meteorlake/romstage/fsp_params.c | 8 |
2 files changed, 19 insertions, 0 deletions
diff --git a/src/soc/intel/meteorlake/chip.h b/src/soc/intel/meteorlake/chip.h index 9d4ff79c61..acb3738f48 100644 --- a/src/soc/intel/meteorlake/chip.h +++ b/src/soc/intel/meteorlake/chip.h @@ -18,6 +18,8 @@ #include <soc/usb.h> #include <stdint.h> +#define MAX_SAGV_POINTS 4 + /* Types of different SKUs */ enum soc_intel_meteorlake_power_limits { MTL_P_282_CORE, @@ -375,6 +377,15 @@ struct soc_intel_meteorlake_config { uint8_t energy_perf_pref_value; bool disable_vmx; + + /* + * SAGV Frequency per point in Mhz. 0 is Auto, otherwise holds the + * frequency value expressed as an integer. For example: 1867 + */ + uint16_t sagv_freq_mhz[MAX_SAGV_POINTS]; + + /* Gear Selection for SAGV points. 0: Auto, 1: Gear 1, 2: Gear 2, 4: Gear 4 */ + uint8_t sagv_gear[MAX_SAGV_POINTS]; }; typedef struct soc_intel_meteorlake_config config_t; diff --git a/src/soc/intel/meteorlake/romstage/fsp_params.c b/src/soc/intel/meteorlake/romstage/fsp_params.c index 38bd443b8f..171009fcaa 100644 --- a/src/soc/intel/meteorlake/romstage/fsp_params.c +++ b/src/soc/intel/meteorlake/romstage/fsp_params.c @@ -123,7 +123,10 @@ static void fill_fspm_igd_params(FSP_M_CONFIG *m_cfg, static void fill_fspm_mrc_params(FSP_M_CONFIG *m_cfg, const struct soc_intel_meteorlake_config *config) { + unsigned int i; + m_cfg->SaGv = config->sagv; + if (m_cfg->SaGv) { /* * Set SaGv work points after reviewing the power and performance impact @@ -134,6 +137,11 @@ static void fill_fspm_mrc_params(FSP_M_CONFIG *m_cfg, m_cfg->SaGvWpMask = config->sagv_wp_bitmap; else m_cfg->SaGvWpMask = SAGV_POINTS_0_1_2_3; + + for (i = 0; i < HOB_MAX_SAGV_POINTS; i++) { + m_cfg->SaGvFreq[i] = config->sagv_freq_mhz[i]; + m_cfg->SaGvGear[i] = config->sagv_gear[i]; + } } m_cfg->RMT = config->rmt; |