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authorNico Huber <nico.h@gmx.de>2018-04-01 01:54:44 +0200
committerNico Huber <nico.h@gmx.de>2019-01-02 21:04:33 +0000
commit9d75e87428c24cbc753a3bc4090dabfe893414b6 (patch)
tree101ea1e57aa29880bf479578aa15215c5bf27618 /src
parent637bef20376b47d9c054d1f77d1583fb7cf67727 (diff)
soc/intel/skylake/graphics: Ensure intel_gma_restore_opregion() is called
Change-Id: If981fa3db12b3a4fe1411f4cce9bac8564697769 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/25466 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Diffstat (limited to 'src')
-rw-r--r--src/soc/intel/skylake/graphics.c17
1 files changed, 8 insertions, 9 deletions
diff --git a/src/soc/intel/skylake/graphics.c b/src/soc/intel/skylake/graphics.c
index 33841b3d8f..e67d82f3b0 100644
--- a/src/soc/intel/skylake/graphics.c
+++ b/src/soc/intel/skylake/graphics.c
@@ -45,6 +45,11 @@ void graphics_soc_init(struct device *dev)
graphics_gtt_write(DDI_BUF_CTL_A, ddi_buf_ctl);
}
+ /* IGD needs to Bus Master */
+ u32 reg32 = pci_read_config32(dev, PCI_COMMAND);
+ reg32 |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO;
+ pci_write_config32(dev, PCI_COMMAND, reg32);
+
/*
* GFX PEIM module inside FSP binary is taking care of graphics
* initialization based on RUN_FSP_GOP Kconfig option and input
@@ -53,15 +58,9 @@ void graphics_soc_init(struct device *dev)
* In case of non-FSP solution, SoC need to select another
* Kconfig to perform GFX initialization.
*/
- if (IS_ENABLED(CONFIG_RUN_FSP_GOP))
- return;
-
- /* IGD needs to Bus Master */
- u32 reg32 = pci_read_config32(dev, PCI_COMMAND);
- reg32 |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO;
- pci_write_config32(dev, PCI_COMMAND, reg32);
-
- if (IS_ENABLED(CONFIG_MAINBOARD_USE_LIBGFXINIT)) {
+ if (IS_ENABLED(CONFIG_RUN_FSP_GOP)) {
+ /* nothing to do */
+ } else if (IS_ENABLED(CONFIG_MAINBOARD_USE_LIBGFXINIT)) {
if (!acpi_is_wakeup_s3() && display_init_required()) {
int lightup_ok;
gma_gfxinit(&lightup_ok);