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authorShuo Liu <shuo.liu@intel.com>2024-10-23 04:20:18 +0800
committerLean Sheng Tan <sheng.tan@9elements.com>2024-11-08 07:21:57 +0000
commit9c7ce22de917deaf2911803caa71d510814ec3c3 (patch)
tree21b9f5eb1f1b1b9c122b2ae748ab07480e456374 /src
parent2c98b3ad235a63ec279990a694f91e32098f3da5 (diff)
soc/intel/xeon_sp/gnr: Enable IRQ routing
Enable IRQ routing per PCH IRQ usage convention and report domain _PRT. Change-Id: I095c7a302894437c90d854ce4e30467357eee2ba Signed-off-by: Lu, Pen-ChunX <pen-chunx.lu@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84328 Reviewed-by: Martin L Roth <gaumless@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src')
-rw-r--r--src/soc/intel/xeon_sp/cpx/Makefile.mk2
-rw-r--r--src/soc/intel/xeon_sp/gnr/Makefile.mk2
-rw-r--r--src/soc/intel/xeon_sp/gnr/soc_acpi.c3
-rw-r--r--src/soc/intel/xeon_sp/lpc.c8
-rw-r--r--src/soc/intel/xeon_sp/lpc_gen1.c12
-rw-r--r--src/soc/intel/xeon_sp/lpc_gen6.c20
-rw-r--r--src/soc/intel/xeon_sp/skx/Makefile.mk2
-rw-r--r--src/soc/intel/xeon_sp/spr/Makefile.mk2
8 files changed, 39 insertions, 12 deletions
diff --git a/src/soc/intel/xeon_sp/cpx/Makefile.mk b/src/soc/intel/xeon_sp/cpx/Makefile.mk
index fca7fe5950..a24b50e035 100644
--- a/src/soc/intel/xeon_sp/cpx/Makefile.mk
+++ b/src/soc/intel/xeon_sp/cpx/Makefile.mk
@@ -11,7 +11,7 @@ romstage-$(CONFIG_DISPLAY_UPD_DATA) += upd_display.c
romstage-$(CONFIG_DISPLAY_HOBS) += hob_display.c
ramstage-y += chip.c cpu.c soc_util.c soc_acpi.c
-ramstage-y += ../chip_gen1.c
+ramstage-y += ../chip_gen1.c ../lpc_gen1.c
ramstage-$(CONFIG_DISPLAY_HOBS) += hob_display.c
ramstage-$(CONFIG_DISPLAY_UPD_DATA) += upd_display.c
diff --git a/src/soc/intel/xeon_sp/gnr/Makefile.mk b/src/soc/intel/xeon_sp/gnr/Makefile.mk
index 1618301411..9b074085d7 100644
--- a/src/soc/intel/xeon_sp/gnr/Makefile.mk
+++ b/src/soc/intel/xeon_sp/gnr/Makefile.mk
@@ -20,7 +20,7 @@ ramstage-y += cpu.c
ramstage-y += soc_util.c
ramstage-y += ramstage.c
ramstage-y += soc_acpi.c
-ramstage-y += ../chip_gen6.c
+ramstage-y += ../chip_gen6.c ../lpc_gen6.c
CPPFLAGS_common += -I$(src)/soc/intel/xeon_sp/gnr/include
CPPFLAGS_common += -I$(src)/soc/intel/xeon_sp/gnr
diff --git a/src/soc/intel/xeon_sp/gnr/soc_acpi.c b/src/soc/intel/xeon_sp/gnr/soc_acpi.c
index 54c0cd2a63..76fabd2af2 100644
--- a/src/soc/intel/xeon_sp/gnr/soc_acpi.c
+++ b/src/soc/intel/xeon_sp/gnr/soc_acpi.c
@@ -84,6 +84,9 @@ void soc_pci_domain_fill_ssdt(const struct device *domain)
acpigen_write_name("_PXM");
acpigen_write_integer(device_to_pd(domain));
+ /* _PRT */
+ acpigen_write_PRT_pre_routed(domain);
+
/* _OSC */
acpigen_write_OSC_pci_domain_fixed_caps(domain,
get_granted_pcie_features(),
diff --git a/src/soc/intel/xeon_sp/lpc.c b/src/soc/intel/xeon_sp/lpc.c
index 7b46564588..bf1deddc36 100644
--- a/src/soc/intel/xeon_sp/lpc.c
+++ b/src/soc/intel/xeon_sp/lpc.c
@@ -17,14 +17,6 @@ void soc_get_gen_io_dec_range(uint32_t gen_io_dec[LPC_NUM_GENERIC_IO_RANGES])
gen_io_dec[3] = config->gen4_dec;
}
-void lpc_soc_init(struct device *dev)
-{
- printk(BIOS_SPEW, "pch: lpc_init\n");
-
- /* FSP configures IOAPIC and PCHInterrupt Config */
- /* Should read back the ID to fill ACPI IOAPIC accordingly. */
-}
-
void pch_lpc_soc_fill_io_resources(struct device *dev)
{
}
diff --git a/src/soc/intel/xeon_sp/lpc_gen1.c b/src/soc/intel/xeon_sp/lpc_gen1.c
new file mode 100644
index 0000000000..9a1c6297fe
--- /dev/null
+++ b/src/soc/intel/xeon_sp/lpc_gen1.c
@@ -0,0 +1,12 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#include <console/console.h>
+#include <intelblocks/lpc_lib.h>
+
+void lpc_soc_init(struct device *dev)
+{
+ printk(BIOS_SPEW, "pch: lpc_init\n");
+
+ /* FSP configures IOAPIC and PCHInterrupt Config */
+ /* Should read back the ID to fill ACPI IOAPIC accordingly. */
+}
diff --git a/src/soc/intel/xeon_sp/lpc_gen6.c b/src/soc/intel/xeon_sp/lpc_gen6.c
new file mode 100644
index 0000000000..d2aaec1888
--- /dev/null
+++ b/src/soc/intel/xeon_sp/lpc_gen6.c
@@ -0,0 +1,20 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#include <console/console.h>
+#include <intelblocks/itss.h>
+#include <intelblocks/lpc_lib.h>
+#include <intelblocks/pcr.h>
+#include <soc/pcr_ids.h>
+
+void lpc_soc_init(struct device *dev)
+{
+ printk(BIOS_SPEW, "pch: lpc_init\n");
+
+ /* Program irq pin/line for PCI devices by PCH convention */
+ pch_pirq_init();
+
+ /* Explicitly set polarity low for PIRQA to PIRQH */
+ for (int i = 0; i < PIRQ_COUNT; i++) {
+ itss_set_irq_polarity(pcr_read8(PID_ITSS, PCR_ITSS_PIRQA_ROUT + i), 1);
+ }
+}
diff --git a/src/soc/intel/xeon_sp/skx/Makefile.mk b/src/soc/intel/xeon_sp/skx/Makefile.mk
index 58d783acb9..456e932fcc 100644
--- a/src/soc/intel/xeon_sp/skx/Makefile.mk
+++ b/src/soc/intel/xeon_sp/skx/Makefile.mk
@@ -16,7 +16,7 @@ romstage-$(CONFIG_DISPLAY_HOBS) += hob_display.c
ramstage-y += soc_acpi.c
ramstage-y += chip.c
-ramstage-y += ../chip_gen1.c
+ramstage-y += ../chip_gen1.c ../lpc_gen1.c
ramstage-y += soc_util.c
ramstage-y += cpu.c
ramstage-$(CONFIG_DISPLAY_UPD_DATA) += upd_display.c
diff --git a/src/soc/intel/xeon_sp/spr/Makefile.mk b/src/soc/intel/xeon_sp/spr/Makefile.mk
index 0c4f0635e3..c5f9ece677 100644
--- a/src/soc/intel/xeon_sp/spr/Makefile.mk
+++ b/src/soc/intel/xeon_sp/spr/Makefile.mk
@@ -15,7 +15,7 @@ romstage-$(CONFIG_DISPLAY_UPD_DATA) += upd_display.c
ramstage-y += chip.c cpu.c soc_util.c ramstage.c soc_acpi.c reset.c
ramstage-y += crashlog.c ioat.c
-ramstage-y += ../chip_gen1.c
+ramstage-y += ../chip_gen1.c ../lpc_gen1.c
ramstage-$(CONFIG_DISPLAY_HOBS) += hob_display.c
ramstage-$(CONFIG_DISPLAY_UPD_DATA) += upd_display.c
CPPFLAGS_common += -I$(src)/soc/intel/xeon_sp/spr/include -I$(src)/soc/intel/xeon_sp/spr