diff options
| author | Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com> | 2022-07-25 22:12:34 -0700 |
|---|---|---|
| committer | Paul Fagerburg <pfagerburg@chromium.org> | 2022-07-27 13:39:25 +0000 |
| commit | 9a690023111144ee0b4b5e8bf3ce7041f51ad155 (patch) | |
| tree | 29b72b23de8a6567ba979fda20beb336f4485b1d /src | |
| parent | 845222f739ae637a45fc4cf2c5a1e8de94f743a6 (diff) | |
soc/intel/meteorlake: Use coreboot native event handler for FSP-S
Beginning FSP 2.2 specifications Fsps Config Upd "FspEventHandler"
was moved to Fsps Arch Upd. Hence we were not seeing Fsps Debug
log was not using coreboot debug library.
This change assigns Fspd Arch Upd FspEventHandler with coreboot
ramstage debug handler when FSP_USES_CB_DEBUG_EVENT_HANDLER
Kconfig is enabled.
Before:
Dumping FSPS_UPD - Size: 0x00001510
0x00000000: 0x41 0x44 0x4C 0x55 0x50 0x44 0x5F 0x53 0x02 0x00 0x00
0x00000010: 0x00
With the fix:
[SPEW ] Dumping FSPS_UPD - Size: 0x00001528
[SPEW ] 0x00000000: 0x41 0x44 0x4C 0x55 0x50 0x44 0x5F 0x53 0x02
[SPEW ] 0x00000010: 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00
[SPEW ] 0x00000020: 0x01 0x00 0x00 0x00 0x20 0x00 0x00 0x00 0xAA
[SPEW ] 0x00000030: 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00
[SPEW ] 0x00000040: 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00
BUG=b:237263080
TEST=Able to build and boot MTL RVP, verified the FSP-S debug
log is using coreboot debug library.
Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com>
Change-Id: Ie63258f6427b3da7927a866bc3767f548b16e3e2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66146
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Diffstat (limited to 'src')
| -rw-r--r-- | src/soc/intel/meteorlake/fsp_params.c | 10 |
1 files changed, 6 insertions, 4 deletions
diff --git a/src/soc/intel/meteorlake/fsp_params.c b/src/soc/intel/meteorlake/fsp_params.c index 39e374b9ae..f918763844 100644 --- a/src/soc/intel/meteorlake/fsp_params.c +++ b/src/soc/intel/meteorlake/fsp_params.c @@ -258,10 +258,6 @@ static void fill_fsps_xdci_params(FSP_S_CONFIG *s_cfg, static void fill_fsps_uart_params(FSP_S_CONFIG *s_cfg, const struct soc_intel_meteorlake_config *config) { - if (CONFIG(FSP_USES_CB_DEBUG_EVENT_HANDLER) && CONFIG(CONSOLE_SERIAL) && - CONFIG(FSP_ENABLE_SERIAL_DEBUG)) - s_cfg->FspEventHandler = (UINT32)((FSP_EVENT_HANDLER *) - fsp_debug_event_handler); ASSERT(ARRAY_SIZE(s_cfg->SerialIoUartAutoFlow) > CONFIG_UART_FOR_CONSOLE); s_cfg->SerialIoUartAutoFlow[CONFIG_UART_FOR_CONSOLE] = 0; } @@ -431,6 +427,12 @@ static void arch_silicon_init_params(FSPS_ARCH_UPD *s_arch_cfg) * EnableMultiPhaseSiliconInit for running MultiPhaseSiInit */ s_arch_cfg->EnableMultiPhaseSiliconInit = 0; + + /* Assign FspEventHandler arch Upd to use coreboot debug event handler */ + if (CONFIG(FSP_USES_CB_DEBUG_EVENT_HANDLER) && CONFIG(CONSOLE_SERIAL) && + CONFIG(FSP_ENABLE_SERIAL_DEBUG)) + s_arch_cfg->FspEventHandler = (FSP_EVENT_HANDLER) + fsp_debug_event_handler; } static void soc_silicon_init_params(FSP_S_CONFIG *s_cfg, |