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authorDuncan Laurie <dlaurie@chromium.org>2013-05-10 11:00:07 -0700
committerAlexandru Gagniuc <mr.nuke.me@gmail.com>2013-11-24 16:11:30 +0100
commit990555b0efafa2860888eeb335477720f464acb2 (patch)
tree2140f74fdcee4f078d824e2997336b8a114533e5 /src
parentfd0bc14844d7ef96781404e4d0a14e522e4f5827 (diff)
haswell: Update GT PM register value
This was changed to 0x80000000 in SA BWG 1.5.0. Change-Id: Ic6773f45057f3eb93b2d93ee543e3db77fccf805 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/50852 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/4166 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Diffstat (limited to 'src')
-rw-r--r--src/northbridge/intel/haswell/gma.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/northbridge/intel/haswell/gma.c b/src/northbridge/intel/haswell/gma.c
index e577fb52f7..f3ddbd3acd 100644
--- a/src/northbridge/intel/haswell/gma.c
+++ b/src/northbridge/intel/haswell/gma.c
@@ -124,7 +124,7 @@ static void gma_pm_init_pre_vbios(struct device *dev)
gtt_write(0x12054, 0x0000000a);
gtt_write(0x22054, 0x0000000a);
- gtt_write(0x0a008, 0x10000000);
+ gtt_write(0x0a008, 0x80000000);
gtt_write(0x0a024, 0x00000b92);
/* Enable RC6 in idle */