diff options
| author | Arthur Heymans <arthur@aheymans.xyz> | 2023-04-19 10:13:44 +0200 |
|---|---|---|
| committer | Lean Sheng Tan <sheng.tan@9elements.com> | 2023-05-13 17:19:27 +0000 |
| commit | 978141171929fd4aaf965dfb60e33f27675d1a54 (patch) | |
| tree | e2c9eff89348298e89844f828ad1fb4fc343e87e /src | |
| parent | a66b469107b10b3013fb1003c4821f0fb666c965 (diff) | |
vendorcode/mediatek/mt8195: More sure ucDoneFlg is initialized
One some codepaths ucDoneFlg is not initialized. This fixes a clang
warning.
Change-Id: I78aa2c711626b24f003f5c95b1c9598eaff7cb1b
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74552
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Diffstat (limited to 'src')
| -rw-r--r-- | src/vendorcode/mediatek/mt8195/dramc/dramc_pi_calibration_api.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/vendorcode/mediatek/mt8195/dramc/dramc_pi_calibration_api.c b/src/vendorcode/mediatek/mt8195/dramc/dramc_pi_calibration_api.c index 6bd1b20928..8496904d11 100644 --- a/src/vendorcode/mediatek/mt8195/dramc/dramc_pi_calibration_api.c +++ b/src/vendorcode/mediatek/mt8195/dramc/dramc_pi_calibration_api.c @@ -3066,7 +3066,7 @@ DRAM_STATUS_T DramcWriteLeveling(DRAMC_CTX_T *p, u8 isAutoK, WLEV_DELAY_BASED_T //U8 *uiLPDDR_O1_Mapping = NULL; //U32 u4value = 0, u4dq_o1 = 0 u4value1 = 0, u4dq_o1_tmp[DQS_BYTE_NUMBER]; - U8 byte_i, rank_i, ucDoneFlg; + U8 byte_i, rank_i, ucDoneFlg = 0; //S32 iDelay, ClockDelayMax; //U8 ucStatus[DQS_BYTE_NUMBER], ucdq_o1[DQS_BYTE_NUMBER], ucdq_o1_shift[DQS_BYTE_NUMBER] //U8 ucHW_cmp_raw_data, uccmp_result[DQS_BYTE_NUMBER]; |