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authorSubrata Banik <subrata.banik@intel.com>2021-06-04 14:09:13 +0530
committerSubrata Banik <subrata.banik@intel.com>2021-06-23 09:08:50 +0000
commit93632a9f1fdbece6cfb1501520005a3c952c8841 (patch)
tree84185cb4ff646eb0024d3eddeb6c5e66bfdaef52 /src
parent194f0eb59c246a4ea0919f13e068e58a0b5779dd (diff)
mb/intel/sm: Skip FSP to program UART0
Set "SerialIoUartMode" for UART0 as PchSerialIoSkipInit Change-Id: Idc7da7bf38634c04b0f4acd4c7c2ea9fa88545e5 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55207 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: V Sowmya <v.sowmya@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src')
-rw-r--r--src/mainboard/intel/shadowmountain/variants/baseboard/devicetree.cb2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/mainboard/intel/shadowmountain/variants/baseboard/devicetree.cb b/src/mainboard/intel/shadowmountain/variants/baseboard/devicetree.cb
index d5e5951c2a..ab2c915488 100644
--- a/src/mainboard/intel/shadowmountain/variants/baseboard/devicetree.cb
+++ b/src/mainboard/intel/shadowmountain/variants/baseboard/devicetree.cb
@@ -103,7 +103,7 @@ chip soc/intel/alderlake
}"
register "SerialIoUartMode" = "{
- [PchSerialIoIndexUART0] = PchSerialIoPci,
+ [PchSerialIoIndexUART0] = PchSerialIoSkipInit,
[PchSerialIoIndexUART1] = PchSerialIoDisabled,
[PchSerialIoIndexUART2] = PchSerialIoDisabled,
}"