diff options
| author | Felix Singer <felixsinger@posteo.net> | 2020-07-25 14:01:52 +0200 |
|---|---|---|
| committer | Michael Niewöhner <c0d3z3r0@review.coreboot.org> | 2020-07-29 20:58:58 +0000 |
| commit | 91dfb920383a8761711e1312f2bcffd2f9529dfb (patch) | |
| tree | c59d0834ada7b19e8dc6699c92697894447b4388 /src | |
| parent | aff69be254096a3a9d630551780c5610b7db15fa (diff) | |
soc/intel/skylake: Enable HECI3 depending on devicetree configuration
Currently HECI3 gets enabled by the option Heci3Enabled, but
this duplicates the devicetree on/off options. Therefore use the
on/off options for the enablement of the HECI3 controller.
I checked all corresponding mainboards if the devicetree configuration
matches the Heci3Enabled setting.
Change-Id: I4f99d434dfee49a9783e38c3910b9391d479cb83
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43864
Reviewed-by: Michael Niewöhner
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src')
| -rw-r--r-- | src/mainboard/intel/kblrvp/variants/rvp11/overridetree.cb | 1 | ||||
| -rw-r--r-- | src/mainboard/intel/saddlebrook/devicetree.cb | 1 | ||||
| -rw-r--r-- | src/soc/intel/skylake/chip.c | 4 | ||||
| -rw-r--r-- | src/soc/intel/skylake/chip.h | 1 |
4 files changed, 3 insertions, 4 deletions
diff --git a/src/mainboard/intel/kblrvp/variants/rvp11/overridetree.cb b/src/mainboard/intel/kblrvp/variants/rvp11/overridetree.cb index bff7967978..b7b569d7cc 100644 --- a/src/mainboard/intel/kblrvp/variants/rvp11/overridetree.cb +++ b/src/mainboard/intel/kblrvp/variants/rvp11/overridetree.cb @@ -7,7 +7,6 @@ chip soc/intel/skylake register "ScsEmmcHs400Enabled" = "0" register "ScsSdCardEnabled" = "0" register "Device4Enable" = "0" - register "Heci3Enabled" = "0" register "PmTimerDisabled" = "0" register "serirq_mode" = "SERIRQ_CONTINUOUS" diff --git a/src/mainboard/intel/saddlebrook/devicetree.cb b/src/mainboard/intel/saddlebrook/devicetree.cb index 944cb50c33..a8066d5cb2 100644 --- a/src/mainboard/intel/saddlebrook/devicetree.cb +++ b/src/mainboard/intel/saddlebrook/devicetree.cb @@ -25,7 +25,6 @@ chip soc/intel/skylake register "ScsSdCardEnabled" = "0" register "SkipExtGfxScan" = "1" register "Device4Enable" = "0" - register "Heci3Enabled" = "0" register "SaGv" = "SaGv_Enabled" register "PmTimerDisabled" = "0" diff --git a/src/soc/intel/skylake/chip.c b/src/soc/intel/skylake/chip.c index 7dee333a6e..a73aa8daab 100644 --- a/src/soc/intel/skylake/chip.c +++ b/src/soc/intel/skylake/chip.c @@ -231,7 +231,9 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) params->PchCio2Enable = config->Cio2Enable; params->SaImguEnable = config->SaImguEnable; - params->Heci3Enabled = config->Heci3Enabled; + + dev = pcidev_path_on_root(PCH_DEVFN_CSE_3); + params->Heci3Enabled = dev ? dev->enabled : 0; params->LogoPtr = config->LogoPtr; params->LogoSize = config->LogoSize; diff --git a/src/soc/intel/skylake/chip.h b/src/soc/intel/skylake/chip.h index 54d006915c..3f55c18b8b 100644 --- a/src/soc/intel/skylake/chip.h +++ b/src/soc/intel/skylake/chip.h @@ -315,7 +315,6 @@ struct soc_intel_skylake_config { u8 PttSwitch; u8 HeciTimeouts; u8 HsioMessaging; - u8 Heci3Enabled; /* Gfx related */ u8 IgdDvmt50PreAlloc; |