diff options
| author | Cliff Huang <cliff.huang@intel.com> | 2023-03-21 21:51:30 -0700 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2023-04-20 22:13:33 +0000 |
| commit | 8fbdefc37fc132d3260a705553be5bf46b56e88c (patch) | |
| tree | d090201ea5c3e1bc8c96b8f6fb6583a32995a2df /src | |
| parent | ad42d9c22baa0ad5abbdb29a7c159b76220404d3 (diff) | |
soc/intel/common/block/pcie/rtd3: Fix source clock check condition for PM method
srcclk_pin is 0-based and '0' is a valid clock source number. If
srcclk_pin is set to -1, then the clock will not be disabled in D3.
Therefore, clock source gating method should not be generated.
BUG=b:271003060
BRANCH=firmware-brya-14505.B
TEST=Boot to OS and check that rtd3 ACPI entries are generated as
expected. For those PCI devices with RTD3 driver whose srcclk_pin to
0, the RTD3 entries should not be missing due to check error.
Signed-off-by: Cliff Huang <cliff.huang@intel.com>
Change-Id: Ia831b8fd17572cc35765bd226d1db470f12ddd41
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73889
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
Diffstat (limited to 'src')
| -rw-r--r-- | src/soc/intel/common/block/pcie/rtd3/rtd3.c | 5 |
1 files changed, 3 insertions, 2 deletions
diff --git a/src/soc/intel/common/block/pcie/rtd3/rtd3.c b/src/soc/intel/common/block/pcie/rtd3/rtd3.c index 8b372ed839..82336d94a9 100644 --- a/src/soc/intel/common/block/pcie/rtd3/rtd3.c +++ b/src/soc/intel/common/block/pcie/rtd3/rtd3.c @@ -419,9 +419,10 @@ static void pcie_rtd3_acpi_fill_ssdt(const struct device *dev) return; } } - if (config->srcclk_pin == 0) { + if (config->srcclk_pin == -1) { if (config->ext_pm_support & ACPI_PCIE_RP_EMIT_SRCK) { - printk(BIOS_ERR, "%s: Can not export SRCK method\n", __func__); + printk(BIOS_ERR, "%s: Can not export SRCK method since clock source gating is not enabled\n", + __func__); return; } } |