diff options
| author | Matt DeVillier <matt.devillier@gmail.com> | 2023-09-17 17:36:23 -0500 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2023-09-22 15:40:08 +0000 |
| commit | 8b126e8b7235641d3003fdd220b0fe2377361035 (patch) | |
| tree | bdf88d8a00a72110941807c46e97c172f8e78e27 /src | |
| parent | 6eb5db39d04d137915232a0b0eba9630244b205c (diff) | |
mb/google/puff: Set early GPIOs to enable bootblock console
Without the PCH UART GPIOs set early, there is no serial console
output until ramstage. Add them to the early GPIOs for all puff
variants.
TEST=build/boot google/puff (wyvern) with serial console enabled,
verify console output starts in bootblock.
Change-Id: Ica0506b2b80e4fac0d3ca11b4cfdd128ce424b36
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78029
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src')
11 files changed, 44 insertions, 0 deletions
diff --git a/src/mainboard/google/puff/variants/ambassador/gpio.c b/src/mainboard/google/puff/variants/ambassador/gpio.c index 996edc4fc7..f50620e358 100644 --- a/src/mainboard/google/puff/variants/ambassador/gpio.c +++ b/src/mainboard/google/puff/variants/ambassador/gpio.c @@ -94,6 +94,10 @@ static const struct pad_config early_gpio_table[] = { PAD_CFG_NF(GPP_B17, NONE, DEEP, NF1), /* B18 : H1_SLAVE_SPI_MOSI_R */ PAD_CFG_NF(GPP_B18, NONE, DEEP, NF1), + /* C8 : UART_PCH_RX_DEBUG_TX */ + PAD_CFG_NF(GPP_C8, NONE, DEEP, NF1), + /* C9 : UART_PCH_TX_DEBUG_RX */ + PAD_CFG_NF(GPP_C9, NONE, DEEP, NF1), /* C14 : BT_DISABLE_L */ PAD_CFG_GPO(GPP_C14, 0, DEEP), /* PCH_WP_OD */ diff --git a/src/mainboard/google/puff/variants/dooly/gpio.c b/src/mainboard/google/puff/variants/dooly/gpio.c index 37cd08cdae..4fd756474b 100644 --- a/src/mainboard/google/puff/variants/dooly/gpio.c +++ b/src/mainboard/google/puff/variants/dooly/gpio.c @@ -131,6 +131,10 @@ static const struct pad_config early_gpio_table[] = { PAD_CFG_NF(GPP_B17, NONE, DEEP, NF1), /* B18 : H1_SLAVE_SPI_MOSI_R */ PAD_CFG_NF(GPP_B18, NONE, DEEP, NF1), + /* C8 : UART_PCH_RX_DEBUG_TX */ + PAD_CFG_NF(GPP_C8, NONE, DEEP, NF1), + /* C9 : UART_PCH_TX_DEBUG_RX */ + PAD_CFG_NF(GPP_C9, NONE, DEEP, NF1), /* C14 : BT_DISABLE_L */ PAD_CFG_GPO(GPP_C14, 0, DEEP), /* PCH_WP_OD */ diff --git a/src/mainboard/google/puff/variants/duffy/gpio.c b/src/mainboard/google/puff/variants/duffy/gpio.c index 996edc4fc7..f50620e358 100644 --- a/src/mainboard/google/puff/variants/duffy/gpio.c +++ b/src/mainboard/google/puff/variants/duffy/gpio.c @@ -94,6 +94,10 @@ static const struct pad_config early_gpio_table[] = { PAD_CFG_NF(GPP_B17, NONE, DEEP, NF1), /* B18 : H1_SLAVE_SPI_MOSI_R */ PAD_CFG_NF(GPP_B18, NONE, DEEP, NF1), + /* C8 : UART_PCH_RX_DEBUG_TX */ + PAD_CFG_NF(GPP_C8, NONE, DEEP, NF1), + /* C9 : UART_PCH_TX_DEBUG_RX */ + PAD_CFG_NF(GPP_C9, NONE, DEEP, NF1), /* C14 : BT_DISABLE_L */ PAD_CFG_GPO(GPP_C14, 0, DEEP), /* PCH_WP_OD */ diff --git a/src/mainboard/google/puff/variants/faffy/gpio.c b/src/mainboard/google/puff/variants/faffy/gpio.c index 996edc4fc7..f50620e358 100644 --- a/src/mainboard/google/puff/variants/faffy/gpio.c +++ b/src/mainboard/google/puff/variants/faffy/gpio.c @@ -94,6 +94,10 @@ static const struct pad_config early_gpio_table[] = { PAD_CFG_NF(GPP_B17, NONE, DEEP, NF1), /* B18 : H1_SLAVE_SPI_MOSI_R */ PAD_CFG_NF(GPP_B18, NONE, DEEP, NF1), + /* C8 : UART_PCH_RX_DEBUG_TX */ + PAD_CFG_NF(GPP_C8, NONE, DEEP, NF1), + /* C9 : UART_PCH_TX_DEBUG_RX */ + PAD_CFG_NF(GPP_C9, NONE, DEEP, NF1), /* C14 : BT_DISABLE_L */ PAD_CFG_GPO(GPP_C14, 0, DEEP), /* PCH_WP_OD */ diff --git a/src/mainboard/google/puff/variants/genesis/gpio.c b/src/mainboard/google/puff/variants/genesis/gpio.c index 66a1b8aec1..4d37923dba 100644 --- a/src/mainboard/google/puff/variants/genesis/gpio.c +++ b/src/mainboard/google/puff/variants/genesis/gpio.c @@ -122,6 +122,10 @@ static const struct pad_config early_gpio_table[] = { PAD_CFG_NF(GPP_B17, NONE, DEEP, NF1), /* B18 : H1_SLAVE_SPI_MOSI_R */ PAD_CFG_NF(GPP_B18, NONE, DEEP, NF1), + /* C8 : UART_PCH_RX_DEBUG_TX */ + PAD_CFG_NF(GPP_C8, NONE, DEEP, NF1), + /* C9 : UART_PCH_TX_DEBUG_RX */ + PAD_CFG_NF(GPP_C9, NONE, DEEP, NF1), /* C14 : BT_DISABLE_L */ PAD_CFG_GPO(GPP_C14, 0, DEEP), /* PCH_WP_OD */ diff --git a/src/mainboard/google/puff/variants/kaisa/gpio.c b/src/mainboard/google/puff/variants/kaisa/gpio.c index 996edc4fc7..f50620e358 100644 --- a/src/mainboard/google/puff/variants/kaisa/gpio.c +++ b/src/mainboard/google/puff/variants/kaisa/gpio.c @@ -94,6 +94,10 @@ static const struct pad_config early_gpio_table[] = { PAD_CFG_NF(GPP_B17, NONE, DEEP, NF1), /* B18 : H1_SLAVE_SPI_MOSI_R */ PAD_CFG_NF(GPP_B18, NONE, DEEP, NF1), + /* C8 : UART_PCH_RX_DEBUG_TX */ + PAD_CFG_NF(GPP_C8, NONE, DEEP, NF1), + /* C9 : UART_PCH_TX_DEBUG_RX */ + PAD_CFG_NF(GPP_C9, NONE, DEEP, NF1), /* C14 : BT_DISABLE_L */ PAD_CFG_GPO(GPP_C14, 0, DEEP), /* PCH_WP_OD */ diff --git a/src/mainboard/google/puff/variants/moonbuggy/gpio.c b/src/mainboard/google/puff/variants/moonbuggy/gpio.c index d8f392028d..2d66d8beda 100644 --- a/src/mainboard/google/puff/variants/moonbuggy/gpio.c +++ b/src/mainboard/google/puff/variants/moonbuggy/gpio.c @@ -134,6 +134,10 @@ static const struct pad_config early_gpio_table[] = { PAD_CFG_NF(GPP_B17, NONE, DEEP, NF1), /* B18 : H1_SLAVE_SPI_MOSI_R */ PAD_CFG_NF(GPP_B18, NONE, DEEP, NF1), + /* C8 : UART_PCH_RX_DEBUG_TX */ + PAD_CFG_NF(GPP_C8, NONE, DEEP, NF1), + /* C9 : UART_PCH_TX_DEBUG_RX */ + PAD_CFG_NF(GPP_C9, NONE, DEEP, NF1), /* C14 : BT_DISABLE_L */ PAD_CFG_GPO(GPP_C14, 0, DEEP), /* C20 : PCH_WP_OD */ diff --git a/src/mainboard/google/puff/variants/noibat/gpio.c b/src/mainboard/google/puff/variants/noibat/gpio.c index 996edc4fc7..f50620e358 100644 --- a/src/mainboard/google/puff/variants/noibat/gpio.c +++ b/src/mainboard/google/puff/variants/noibat/gpio.c @@ -94,6 +94,10 @@ static const struct pad_config early_gpio_table[] = { PAD_CFG_NF(GPP_B17, NONE, DEEP, NF1), /* B18 : H1_SLAVE_SPI_MOSI_R */ PAD_CFG_NF(GPP_B18, NONE, DEEP, NF1), + /* C8 : UART_PCH_RX_DEBUG_TX */ + PAD_CFG_NF(GPP_C8, NONE, DEEP, NF1), + /* C9 : UART_PCH_TX_DEBUG_RX */ + PAD_CFG_NF(GPP_C9, NONE, DEEP, NF1), /* C14 : BT_DISABLE_L */ PAD_CFG_GPO(GPP_C14, 0, DEEP), /* PCH_WP_OD */ diff --git a/src/mainboard/google/puff/variants/puff/gpio.c b/src/mainboard/google/puff/variants/puff/gpio.c index 996edc4fc7..f50620e358 100644 --- a/src/mainboard/google/puff/variants/puff/gpio.c +++ b/src/mainboard/google/puff/variants/puff/gpio.c @@ -94,6 +94,10 @@ static const struct pad_config early_gpio_table[] = { PAD_CFG_NF(GPP_B17, NONE, DEEP, NF1), /* B18 : H1_SLAVE_SPI_MOSI_R */ PAD_CFG_NF(GPP_B18, NONE, DEEP, NF1), + /* C8 : UART_PCH_RX_DEBUG_TX */ + PAD_CFG_NF(GPP_C8, NONE, DEEP, NF1), + /* C9 : UART_PCH_TX_DEBUG_RX */ + PAD_CFG_NF(GPP_C9, NONE, DEEP, NF1), /* C14 : BT_DISABLE_L */ PAD_CFG_GPO(GPP_C14, 0, DEEP), /* PCH_WP_OD */ diff --git a/src/mainboard/google/puff/variants/scout/gpio.c b/src/mainboard/google/puff/variants/scout/gpio.c index 55154364ac..6bd963727b 100644 --- a/src/mainboard/google/puff/variants/scout/gpio.c +++ b/src/mainboard/google/puff/variants/scout/gpio.c @@ -156,6 +156,10 @@ static const struct pad_config early_gpio_table[] = { PAD_CFG_NF(GPP_B17, NONE, DEEP, NF1), /* B18 : H1_SLAVE_SPI_MOSI_R */ PAD_CFG_NF(GPP_B18, NONE, DEEP, NF1), + /* C8 : UART_PCH_RX_DEBUG_TX */ + PAD_CFG_NF(GPP_C8, NONE, DEEP, NF1), + /* C9 : UART_PCH_TX_DEBUG_RX */ + PAD_CFG_NF(GPP_C9, NONE, DEEP, NF1), /* C14 : BT_DISABLE_L */ PAD_CFG_GPO(GPP_C14, 0, DEEP), /* PCH_WP_OD */ diff --git a/src/mainboard/google/puff/variants/wyvern/gpio.c b/src/mainboard/google/puff/variants/wyvern/gpio.c index 996edc4fc7..f50620e358 100644 --- a/src/mainboard/google/puff/variants/wyvern/gpio.c +++ b/src/mainboard/google/puff/variants/wyvern/gpio.c @@ -94,6 +94,10 @@ static const struct pad_config early_gpio_table[] = { PAD_CFG_NF(GPP_B17, NONE, DEEP, NF1), /* B18 : H1_SLAVE_SPI_MOSI_R */ PAD_CFG_NF(GPP_B18, NONE, DEEP, NF1), + /* C8 : UART_PCH_RX_DEBUG_TX */ + PAD_CFG_NF(GPP_C8, NONE, DEEP, NF1), + /* C9 : UART_PCH_TX_DEBUG_RX */ + PAD_CFG_NF(GPP_C9, NONE, DEEP, NF1), /* C14 : BT_DISABLE_L */ PAD_CFG_GPO(GPP_C14, 0, DEEP), /* PCH_WP_OD */ |