soc/intel/cnl: use Kconfig to determine PCH type

We already know the PCH type at build time, so there is no need to do
runtime detection. Thus, use Kconfig and drop `get_pch_series()`.

Change-Id: I470871af5f5954e91a8135fddf4a2297a514d740
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49874
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

4 files changed, 2 insertions, 48 deletions

diff --git a/src/soc/intel/cannonlake/bootblock/pch.c b/src/soc/intel/cannonlake/bootblock/pch.c
index a05e56549c..f4208450b3 100644
--- a/src/soc/intel/cannonlake/bootblock/pch.c
+++ b/src/soc/intel/cannonlake/bootblock/pch.c
@@ -43,16 +43,10 @@
 
 static uint32_t get_pmc_reg_base(void)
 {
-	uint8_t pch_series;
-
-	pch_series = get_pch_series();
-
-	if (pch_series == PCH_H)
+	if (CONFIG(SOC_INTEL_CANNONLAKE_PCH_H))
 		return PCR_PSF3_TO_SHDW_PMC_REG_BASE_CNP_H;
-	else if (pch_series == PCH_LP)
-		return PCR_PSF3_TO_SHDW_PMC_REG_BASE_CNP_LP;
 	else
-		return 0;
+		return PCR_PSF3_TO_SHDW_PMC_REG_BASE_CNP_LP;
 }
 
 static void soc_config_pwrmbase(void)
diff --git a/src/soc/intel/cannonlake/include/soc/lpc.h b/src/soc/intel/cannonlake/include/soc/lpc.h
index c52bc9f5ec..a510bc51a9 100644
--- a/src/soc/intel/cannonlake/include/soc/lpc.h
+++ b/src/soc/intel/cannonlake/include/soc/lpc.h
@@ -31,15 +31,4 @@
 #define PCCTL			0xE0 /* PCI Clock Control */
 #define   CLKRUN_EN		(1 << 0)
 
-/*
- * This function will help to differentiate between 2 PCH on single type of soc.
- * Since same soc may have LP series pch or H series PCH, we need to
- * differentiate by reading upper 8 bits of PCH device ids.
- *
- * Return:
- *	Return PCH_LP or PCH_H macro in case of respective device ID found.
- *	PCH_UNKNOWN_SERIES in case of invalid device ID.
- */
-uint8_t get_pch_series(void);
-
 #endif
diff --git a/src/soc/intel/cannonlake/include/soc/pch.h b/src/soc/intel/cannonlake/include/soc/pch.h
index e4fd36de33..768655f758 100644
--- a/src/soc/intel/cannonlake/include/soc/pch.h
+++ b/src/soc/intel/cannonlake/include/soc/pch.h
@@ -3,10 +3,6 @@
 #ifndef _SOC_CANNONLAKE_PCH_H_
 #define _SOC_CANNONLAKE_PCH_H_
 
-#define PCH_H				1
-#define PCH_LP				2
-#define PCH_UNKNOWN_SERIES		0xFF
-
 #define PCIE_CLK_NOTUSED		0xFF
 #define PCIE_CLK_LAN			0x70
 #define PCIE_CLK_FREE			0x80
diff --git a/src/soc/intel/cannonlake/lpc.c b/src/soc/intel/cannonlake/lpc.c
index 26bda70845..b03f21e2a2 100644
--- a/src/soc/intel/cannonlake/lpc.c
+++ b/src/soc/intel/cannonlake/lpc.c
@@ -37,31 +37,6 @@ void soc_setup_dmi_pcr_io_dec(uint32_t *gen_io_dec)
 	pcr_write32(PID_DMI, PCR_DMI_LPCLGIR4, gen_io_dec[3]);
 }
 
-uint8_t get_pch_series(void)
-{
-	uint16_t lpc_did_hi_byte;
-	uint8_t pch_series = PCH_UNKNOWN_SERIES;
-	/*
-	 * Fetch upper 8 bits on LPC device ID to determine PCH type
-	 * Adding 1 to the offset to fetch upper 8 bits
-	 */
-	lpc_did_hi_byte = pci_read_config8(PCH_DEV_LPC, PCI_DEVICE_ID + 1);
-
-	switch (lpc_did_hi_byte) {
-	case 0x9D: /* CNL-LP */
-	case 0x02: /* CML-LP */
-		pch_series = PCH_LP;
-		break;
-	case 0xA3: /* CFL-H */
-	case 0x06: /* CML-H */
-		pch_series = PCH_H;
-		break;
-	default:
-		break;
-	}
-	return pch_series;
-}
-
 #if ENV_RAMSTAGE
 static void soc_mirror_dmi_pcr_io_dec(void)
 {