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authorSunwei Li <lisunwei@huaqin.corp-partner.google.com>2021-09-10 15:36:32 +0800
committerFelix Held <felix-coreboot@felixheld.de>2021-09-16 15:38:33 +0000
commit86f0df4ca20bf69e773da2656d5526e4bf8aa076 (patch)
tree5171d30239160d4924e41379fffbe5320a0fb29a /src
parenta90acbd6ddf979907d8afce2f56350862ef4427b (diff)
mb/google/dedede/var/cappy2: Configure I2C times for tp & codec
Configure I2C high / low time in the device tree to ensure I2C CLK runs accurately between 380 kHz and 400 kHz. Measured I2C frequency just as below after tuning: touchpad:390kHz codec:395.8kHz BUG=b:199481261 BRANCH=dedede TEST=Build and check after tuning I2C clock is between 380 kHz and 400 kHz Signed-off-by: Sunwei Li <lisunwei@huaqin.corp-partner.google.com> Change-Id: Ifadc3d19eb57fe6f67504be154c30df7bc0fee71 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57551 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Diffstat (limited to 'src')
-rw-r--r--src/mainboard/google/dedede/variants/cappy2/overridetree.cb4
1 files changed, 4 insertions, 0 deletions
diff --git a/src/mainboard/google/dedede/variants/cappy2/overridetree.cb b/src/mainboard/google/dedede/variants/cappy2/overridetree.cb
index 7519a326ff..7e95edae0a 100644
--- a/src/mainboard/google/dedede/variants/cappy2/overridetree.cb
+++ b/src/mainboard/google/dedede/variants/cappy2/overridetree.cb
@@ -22,6 +22,8 @@ chip soc/intel/jasperlake
register "common_soc_config" = "{
.i2c[0] = {
.speed = I2C_SPEED_FAST,
+ .rise_time_ns = 255,
+ .fall_time_ns = 14,
},
.i2c[1] = {
.speed = I2C_SPEED_FAST,
@@ -34,6 +36,8 @@ chip soc/intel/jasperlake
},
.i2c[4] = {
.speed = I2C_SPEED_FAST,
+ .rise_time_ns = 105,
+ .fall_time_ns = 4,
},
}"