diff options
| author | Felix Held <felix-coreboot@felixheld.de> | 2019-12-30 17:27:59 +0100 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2020-01-01 16:08:45 +0000 |
| commit | 85e1491eba241adcebe9c0a65dd5d5b85c0a6928 (patch) | |
| tree | 94793a1159cb468c1be4e4dbd74506c85e2684ba /src | |
| parent | 651f99f12b48729a2a786240679f9aeafcf1cf8b (diff) | |
nb/intel/sandybridge: move MCHBAR register definitions to sandybridge.h
Change-Id: Ibce9f043d3b3fa9acd297f4130bda7a3c595aaa0
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38009
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Diffstat (limited to 'src')
| -rw-r--r-- | src/northbridge/intel/sandybridge/raminit_common.h | 4 | ||||
| -rw-r--r-- | src/northbridge/intel/sandybridge/sandybridge.h | 7 |
2 files changed, 5 insertions, 6 deletions
diff --git a/src/northbridge/intel/sandybridge/raminit_common.h b/src/northbridge/intel/sandybridge/raminit_common.h index 317071c707..6bbc8b3e0f 100644 --- a/src/northbridge/intel/sandybridge/raminit_common.h +++ b/src/northbridge/intel/sandybridge/raminit_common.h @@ -149,10 +149,6 @@ typedef struct ramctr_timing_st { #define MAKE_ERR ((channel<<16)|(slotrank<<8)|1) #define GET_ERR_CHANNEL(x) (x>>16) -#define MC_BIOS_REQ 0x5e00 -#define MC_BIOS_DATA 0x5e04 -#define PM_PDWN_Config 0x4cb0 - u8 get_CWL(u32 tCK); void dram_mrscommands(ramctr_timing * ctrl); void program_timings(ramctr_timing * ctrl, int channel); diff --git a/src/northbridge/intel/sandybridge/sandybridge.h b/src/northbridge/intel/sandybridge/sandybridge.h index 6a9c00f396..a0fcb104e0 100644 --- a/src/northbridge/intel/sandybridge/sandybridge.h +++ b/src/northbridge/intel/sandybridge/sandybridge.h @@ -127,8 +127,11 @@ enum platform_type { #define MCHBAR32_AND_OR(x, and, or) \ (MCHBAR32(x) = (MCHBAR32(x) & (and)) | (or)) -#define SSKPD 0x5d14 /* 16bit (scratchpad) */ -#define BIOS_RESET_CPL 0x5da8 /* 8bit */ +#define PM_PDWN_Config 0x4cb0 +#define MC_BIOS_REQ 0x5e00 +#define MC_BIOS_DATA 0x5e04 +#define SSKPD 0x5d14 /* 16bit (scratchpad) */ +#define BIOS_RESET_CPL 0x5da8 /* 8bit */ /* * EPBAR - Egress Port Root Complex Register Block |