summaryrefslogtreecommitdiff
path: root/src
diff options
context:
space:
mode:
authorThejaswani Putta <thejaswani.putta@intel.com>2021-07-30 12:38:37 -0700
committerTim Wawrzynczak <twawrzynczak@chromium.org>2021-08-03 21:47:05 +0000
commit8239d076bf461413589303c615682004e613e21b (patch)
tree4d1db92ac38dd750e856ad5ec6cd000b1de0f608 /src
parente8cd480046b2f8660c52d5503d5cc0cd4a5cd002 (diff)
mb/google/brya: Add RTD3 for WWAN
Enable the PCIe RTD3 driver for WWAN device attached to PCIe Root Port 6 and provide the reset GPIO / src clk pins. BUG=None BRANCH=None TEST=Build and boot the coreboot image, check if device is enumerated in the lspci list after warm/cold reboot cycles, run suspend cycles and check if WWAN is entering L2 LPM. Signed-off-by: Thejaswani Putta <thejaswani.putta@intel.com> Change-Id: Ie9d1ce55cc1297ea0e1069979bbecfaac8f8de05 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56722 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
Diffstat (limited to 'src')
-rw-r--r--src/mainboard/google/brya/variants/baseboard/brya/devicetree.cb5
1 files changed, 5 insertions, 0 deletions
diff --git a/src/mainboard/google/brya/variants/baseboard/brya/devicetree.cb b/src/mainboard/google/brya/variants/baseboard/brya/devicetree.cb
index 12bff55b68..b8d0b5c173 100644
--- a/src/mainboard/google/brya/variants/baseboard/brya/devicetree.cb
+++ b/src/mainboard/google/brya/variants/baseboard/brya/devicetree.cb
@@ -140,6 +140,11 @@ chip soc/intel/alderlake
device ref sata on end
device ref pcie_rp6 on
# Enable WWAN PCIE 6 using clk 5
+ chip soc/intel/common/block/pcie/rtd3
+ register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_E0)"
+ register "srcclk_pin" = "5"
+ device generic 0 on end
+ end
register "pch_pcie_rp[PCH_RP(6)]" = "{
.clk_src = 5,
.clk_req = 5,