diff options
| author | Paul Menzel <pmenzel@molgen.mpg.de> | 2021-12-15 10:47:05 +0100 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2021-12-16 14:17:36 +0000 |
| commit | 7f5a1eeb24b6e3523d836cb0d3533fbb12f9fdf3 (patch) | |
| tree | c1cfed28bc081c572f52fdc4933628d050b9c8f8 /src | |
| parent | 74d2218cc7c5b9d07528a2ffb3b727e52e688bd3 (diff) | |
Spell *Boot Guard* with a space for official spelling
See for example Intel document *Secure the Network Infrastructure –
Secure Boot Methodologies* [1].
Change all occurrences with the command below:
$ git grep -l BootGuard | xargs sed -i 's/BootGuard/Boot Guard/g'
[1]: https://builders.intel.com/docs/networkbuilders/secure-the-network-infrastructure-secure-boot-methodologies.pdf
Change-Id: I69fb64b525fb4799bcb9d75624003c0d59b885b5
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60136
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Diffstat (limited to 'src')
| -rw-r--r-- | src/lib/Kconfig.cbfs_verification | 2 | ||||
| -rw-r--r-- | src/northbridge/intel/haswell/northbridge.c | 2 | ||||
| -rw-r--r-- | src/soc/intel/broadwell/northbridge.c | 2 |
3 files changed, 3 insertions, 3 deletions
diff --git a/src/lib/Kconfig.cbfs_verification b/src/lib/Kconfig.cbfs_verification index 33e5458650..9a9ba3189d 100644 --- a/src/lib/Kconfig.cbfs_verification +++ b/src/lib/Kconfig.cbfs_verification @@ -13,7 +13,7 @@ config CBFS_VERIFICATION file as it gets loaded by chaining it to a trust anchor that is embedded in the bootblock. This only makes sense if you use some out-of-band mechanism to guarantee the integrity of the bootblock - itself, such as Intel BootGuard or flash write-protection. + itself, such as Intel Boot Guard or flash write-protection. If a CBFS image was created with this option enabled, cbfstool will automatically update the hash embedded in the bootblock whenever it diff --git a/src/northbridge/intel/haswell/northbridge.c b/src/northbridge/intel/haswell/northbridge.c index 9ead46bc98..fd5ffd9579 100644 --- a/src/northbridge/intel/haswell/northbridge.c +++ b/src/northbridge/intel/haswell/northbridge.c @@ -247,7 +247,7 @@ static void mc_add_dram_resources(struct device *dev, int *resource_cnt) /* * DMA Protected Range can be reserved below TSEG for PCODE patch - * or TXT/BootGuard related data. Rather than report a base address, + * or TXT/Boot Guard related data. Rather than report a base address, * the DPR register reports the TOP of the region, which is the same * as TSEG base. The region size is reported in MiB in bits 11:4. */ diff --git a/src/soc/intel/broadwell/northbridge.c b/src/soc/intel/broadwell/northbridge.c index 76ea35f87a..4511c07502 100644 --- a/src/soc/intel/broadwell/northbridge.c +++ b/src/soc/intel/broadwell/northbridge.c @@ -272,7 +272,7 @@ static void mc_add_dram_resources(struct device *dev, int *resource_cnt) /* * DMA Protected Range can be reserved below TSEG for PCODE patch - * or TXT/BootGuard related data. Rather than report a base address + * or TXT/Boot Guard related data. Rather than report a base address * the DPR register reports the TOP of the region, which is the same * as TSEG base. The region size is reported in MiB in bits 11:4. */ |