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authorDuncan Laurie <dlaurie@google.com>2020-11-05 10:09:58 -0800
committerDuncan Laurie <dlaurie@chromium.org>2020-11-20 00:25:37 +0000
commit7d9713674956bbd055631d6fe5f67922a5823c3a (patch)
treee89a8aeed151f1de44c33037ab7b51be77c2b367 /src
parent17e905ac48dd30cd7edf3dbad57415f5523c9364 (diff)
soc/intel/tigerlake: Enable GPIO IOSTANDBY configuration
Enable SOC_INTEL_COMMON_BLOCK_GPIO_IOSTANDBY so the pads can be configured with non-zero IOSSTATE values. BUG=b:171993054 Signed-off-by: Duncan Laurie <dlaurie@google.com> Change-Id: I1f895dbdbb71a353a98272db6dc70b54e8e172a3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/47254 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src')
-rw-r--r--src/soc/intel/tigerlake/Kconfig1
1 files changed, 1 insertions, 0 deletions
diff --git a/src/soc/intel/tigerlake/Kconfig b/src/soc/intel/tigerlake/Kconfig
index e117842e7f..e962e4cccc 100644
--- a/src/soc/intel/tigerlake/Kconfig
+++ b/src/soc/intel/tigerlake/Kconfig
@@ -48,6 +48,7 @@ config CPU_SPECIFIC_OPTIONS
select SOC_INTEL_COMMON_BLOCK_CPU_MPINIT
select SOC_INTEL_COMMON_BLOCK_DTT
select SOC_INTEL_COMMON_BLOCK_GPIO_DUAL_ROUTE_SUPPORT
+ select SOC_INTEL_COMMON_BLOCK_GPIO_IOSTANDBY
select SOC_INTEL_COMMON_BLOCK_GSPI_VERSION_2
select SOC_INTEL_COMMON_BLOCK_HDA
select SOC_INTEL_COMMON_BLOCK_PCIE_RTD3