diff options
| author | Subrata Banik <subrata.banik@intel.com> | 2018-01-10 11:01:32 +0530 |
|---|---|---|
| committer | Subrata Banik <subrata.banik@intel.com> | 2018-01-17 17:47:48 +0000 |
| commit | 71a5138807e529f2b3ca29fc1caf0408270b3d3d (patch) | |
| tree | f27849c1a90abb0e7b73c980f2a1d91424a3ec32 /src | |
| parent | 888520622b65bc0eabd55d04c314ffc1b0ed5b7e (diff) | |
soc/intel/cannonlake: Reserve PMC IO resources
PMC controller gets hidden during FSP Silicon initialization
using sideband interface on CNP-PCH. Hence unable to reserve
PMC IO resources during PCI enumeration process. This causes
hang issue on non-chrome platform with CNP-PCH due to ABASE
corruption.
This patch ensures PMC IO resource (ABASE) is getting reserved
(IO address 0x1800-0x1900) and ACPI base is not overwritten by
other devices.
TEST=ABASE range is reserved along with LPC IO range during PCI
enumeration.
PCI: 00:1f.0 resource base 1800 size 100 align 0 gran 0 limit 0
flags c0000100 index 20
Change-Id: I1fbc4339ae11058fb3daedf4ffedda1904fa52ec
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/23202
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src')
| -rw-r--r-- | src/soc/intel/cannonlake/lpc.c | 18 |
1 files changed, 18 insertions, 0 deletions
diff --git a/src/soc/intel/cannonlake/lpc.c b/src/soc/intel/cannonlake/lpc.c index 60729f144a..c02d66e54d 100644 --- a/src/soc/intel/cannonlake/lpc.c +++ b/src/soc/intel/cannonlake/lpc.c @@ -203,4 +203,22 @@ void lpc_soc_init(struct device *dev) i8259_configure_irq_trigger(9, 1); clock_gate_8254(dev); } + +/* Fill up LPC IO resource structure inside SoC directory */ +void pch_lpc_soc_fill_io_resources(struct device *dev) +{ + /* + * PMC pci device gets hidden from PCI bus due to Silicon + * policy hence bind ACPI BASE aka ABASE (offset 0x20) with + * LPC IO resources to ensure that ABASE falls under PCI reserved + * IO memory range. + * + * Note: Don't add any more resource with same offset 0x20 + * under this device space. + */ + pch_lpc_add_new_resource(dev, PCI_BASE_ADDRESS_4, + ACPI_BASE_ADDRESS, ACPI_BASE_SIZE, IORESOURCE_IO | + IORESOURCE_ASSIGNED | IORESOURCE_FIXED); +} + #endif |