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authorMatt DeVillier <matt.devillier@gmail.com>2020-03-24 15:39:34 -0500
committerMatt DeVillier <matt.devillier@gmail.com>2020-03-29 18:00:20 +0000
commit6e50849b8cd88e481e5460e4333cb3f198c89d0c (patch)
tree7ac19ae89bb909449542e98c4da0971c25420d39 /src
parentb49e210984c4e44669e1335f97f32c83ff948a31 (diff)
mb/51nb/x210: Fix up USB ports in devicetree
Add missing port definition for the mSATA/WWAN mPCIe port, set OC pin for internal ports to OC_SKIP, fix port descrption for mPCIe/WLAN port, remove USB3 definition for right type-A port as it is USB2 only. Test: insert WiFi module into WWAN port, observe BT portion detected and functional. Change-Id: Ie39b99eeb0f605ff07d57c32189fb1f4183713e4 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39808 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Diffstat (limited to 'src')
-rw-r--r--src/mainboard/51nb/x210/devicetree.cb13
1 files changed, 6 insertions, 7 deletions
diff --git a/src/mainboard/51nb/x210/devicetree.cb b/src/mainboard/51nb/x210/devicetree.cb
index ee6e5ffd59..50d217d170 100644
--- a/src/mainboard/51nb/x210/devicetree.cb
+++ b/src/mainboard/51nb/x210/devicetree.cb
@@ -107,16 +107,15 @@ chip soc/intel/skylake
register "usb2_ports[0]" = "USB2_PORT_MID(OC1)" # Type-A Port (left)
register "usb2_ports[1]" = "USB2_PORT_MID(OC1)" # Type-A Port (left)
- register "usb2_ports[2]" = "USB2_PORT_FLEX(OC1)" # FPR
- register "usb2_ports[3]" = "USB2_PORT_FLEX(OC1)" # SD
- register "usb2_ports[4]" = "USB2_PORT_FLEX(OC1)" # INT
+ register "usb2_ports[2]" = "USB2_PORT_FLEX(OC_SKIP)" # FPR
+ register "usb2_ports[3]" = "USB2_PORT_FLEX(OC_SKIP)" # SD
+ register "usb2_ports[4]" = "USB2_PORT_FLEX(OC_SKIP)" # INT
register "usb2_ports[5]" = "USB2_PORT_MID(OC1)" # Type-A Port (right)
- register "usb2_ports[6]" = "USB2_PORT_FLEX(OC2)" # Webcam
- register "usb2_ports[7]" = "USB2_PORT_FLEX(OC2)" # M.2-2230 USB (BT)
+ register "usb2_ports[6]" = "USB2_PORT_FLEX(OC_SKIP)" # Webcam
+ register "usb2_ports[7]" = "USB2_PORT_MID(OC_SKIP)" # mPCIe / WiFi Port
+ register "usb2_ports[8]" = "USB2_PORT_MID(OC_SKIP)" # mSATA / WWAN Port
register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC1)" # Type-A Port (left)
- register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC1)" # Type-A Port (left)
- register "usb3_ports[5]" = "USB3_PORT_DEFAULT(OC1)" # Type-A Port (right)
# PL1 override 25W
register "tdp_pl1_override" = "25"