diff options
| author | Julius Werner <jwerner@chromium.org> | 2020-10-12 15:32:52 -0700 |
|---|---|---|
| committer | Julius Werner <jwerner@chromium.org> | 2020-10-13 22:41:05 +0000 |
| commit | 6b8305d24054a452716b748e406c0263607d3bcb (patch) | |
| tree | 1a7ad953ba92409c7a1517dc23113a433737221f /src | |
| parent | b73d2476dc2c52ec3310ee50b86b25186f98d25c (diff) | |
drivers: snsn65dsi86: Fix link rate parsing
DP link rates are reported in an array of LE16 values. The current code
tries to parse them as 8-bit which doesn't get very far, causing us to
always drop into the fallback path. This patch should fix the issue
(+minor whitespace cleanup).
BUG=b:170630766
Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: I1e03088ee2d3517bdb5dcc4dcc4ac04f8b14a391
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46318
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Douglas Anderson <dianders@chromium.org>
Diffstat (limited to 'src')
| -rw-r--r-- | src/drivers/ti/sn65dsi86bridge/sn65dsi86bridge.c | 12 |
1 files changed, 5 insertions, 7 deletions
diff --git a/src/drivers/ti/sn65dsi86bridge/sn65dsi86bridge.c b/src/drivers/ti/sn65dsi86bridge/sn65dsi86bridge.c index 5a6eb496ea..44a80884aa 100644 --- a/src/drivers/ti/sn65dsi86bridge/sn65dsi86bridge.c +++ b/src/drivers/ti/sn65dsi86bridge/sn65dsi86bridge.c @@ -259,11 +259,11 @@ static void sn65dsi86_bridge_valid_dp_rates(uint8_t bus, uint8_t chip, bool rate DP_BRIDGE_DPCD_REV, 1, DPCD_READ, &dpcd_val); if (dpcd_val >= DP_BRIDGE_14) { /* eDP 1.4 devices must provide a custom table */ - uint8_t sink_rates[DP_MAX_SUPPORTED_RATES * 2]; + uint16_t sink_rates[DP_MAX_SUPPORTED_RATES] = {0}; sn65dsi86_bridge_dpcd_request(bus, chip, DP_SUPPORTED_LINK_RATES, sizeof(sink_rates), - DPCD_READ, sink_rates); + DPCD_READ, (void *)sink_rates); for (i = 0; i < ARRAY_SIZE(sink_rates); i++) { rate_per_200khz = le16_to_cpu(sink_rates[i]); @@ -288,14 +288,12 @@ static void sn65dsi86_bridge_valid_dp_rates(uint8_t bus, uint8_t chip, bool rate } /* On older versions best we can do is use DP_MAX_LINK_RATE */ - sn65dsi86_bridge_dpcd_request(bus, chip, - DP_MAX_LINK_RATE, 1, DPCD_READ, &dpcd_val); + sn65dsi86_bridge_dpcd_request(bus, chip, DP_MAX_LINK_RATE, 1, DPCD_READ, &dpcd_val); switch (dpcd_val) { default: - printk(BIOS_ERR, - "Unexpected max rate (%#x); assuming 5.4 GHz\n", - (int)dpcd_val); + printk(BIOS_ERR, "Unexpected max rate (%#x); assuming 5.4 GHz\n", + (int)dpcd_val); /* fall through */ case DP_LINK_BW_5_4: rate_valid[7] = 1; |