soc/intel/braswell: Use common sb code for SPI lockdown configuration

This removes the weakly linked function to configure the SPI lockdown.

Change-Id: I1e7be41a9470b37ad954d3120a67fc4d93633113
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36007
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

6 files changed, 22 insertions, 194 deletions

diff --git a/src/mainboard/facebook/fbg1701/w25q64.c b/src/mainboard/facebook/fbg1701/w25q64.c
index bc908f04b3..2f131f4ec6 100644
--- a/src/mainboard/facebook/fbg1701/w25q64.c
+++ b/src/mainboard/facebook/fbg1701/w25q64.c
@@ -20,57 +20,16 @@
 #include <drivers/spi/spi_winbond.h>
 
 /*
- * SPI lockdown configuration
+ * SPI VSCC configuration
  */
-#define SPI_OPMENU_0	CMD_W25_WRSR		/* Write Status Register */
-#define SPI_OPTYPE_0	SPI_OPTYPE_WR_NOADDR	/* Write, no address */
-
-#define SPI_OPMENU_1	CMD_W25_PP		/* BYPR: Byte Program */
-#define SPI_OPTYPE_1	SPI_OPTYPE_WR_ADDR	/* Write, address required */
-
-#define SPI_OPMENU_2	CMD_W25_READ		/* Read Data */
-#define SPI_OPTYPE_2	SPI_OPTYPE_RD_ADDR	/* Read, address required */
-
-#define SPI_OPMENU_3	CMD_W25_RDSR		/* Read Status Register */
-#define SPI_OPTYPE_3	SPI_OPTYPE_RD_NOADDR	/* Read, no address */
-
-#define SPI_OPMENU_4	CMD_W25_SE		/* Sector Erase */
-#define SPI_OPTYPE_4	SPI_OPTYPE_WR_ADDR	/* Write, address required */
-
-#define SPI_OPMENU_5	CMD_W25_RDID		/* Read ID */
-#define SPI_OPTYPE_5	SPI_OPTYPE_RD_NOADDR	/* Read, no address */
-
-#define SPI_OPMENU_6	CMD_W25_BE		/* BE: Block Erase */
-#define SPI_OPTYPE_6	SPI_OPTYPE_WR_ADDR	/* Write, address required */
-
-#define SPI_OPMENU_7	CMD_W25_FAST_READ	/* FAST: Fast Read */
-#define SPI_OPTYPE_7	SPI_OPTYPE_RD_ADDR	/* Read, address required */
-
-#define SPI_OPPREFIX	CMD_W25_WREN		/* WREN only to be inline */
-						/* with flashrom */
-
-#define SPI_OPTYPE ((SPI_OPTYPE_7 << 14) | (SPI_OPTYPE_6 << 12) | \
-		    (SPI_OPTYPE_5 << 10) | (SPI_OPTYPE_4 <<  8) | \
-		    (SPI_OPTYPE_3 <<  6) | (SPI_OPTYPE_2 <<  4) | \
-		    (SPI_OPTYPE_1 <<  2) | (SPI_OPTYPE_0 <<  0))
-
-#define SPI_OPMENU_UPPER ((SPI_OPMENU_7 << 24) | (SPI_OPMENU_6 << 16) | \
-			  (SPI_OPMENU_5 <<  8) | (SPI_OPMENU_4 <<  0))
-
-#define SPI_OPMENU_LOWER ((SPI_OPMENU_3 << 24) | (SPI_OPMENU_2 << 16) | \
-			  (SPI_OPMENU_1 <<  8) | (SPI_OPMENU_0 <<  0))
-
 #define SPI_VSCC (WG_64_BYTE | EO(0x20) | BES_4_KB)
 
-static const struct spi_config spi_config = {
-	.preop = CMD_W25_WREN,
-	.optype = SPI_OPTYPE,
-	.opmenu = { SPI_OPMENU_LOWER, SPI_OPMENU_UPPER },
+static const struct vscc_config spi_config = {
 	.lvscc =  SPI_VSCC,
 	.uvscc =  SPI_VSCC,
 };
 
-int mainboard_get_spi_config(struct spi_config *cfg)
+int mainboard_get_spi_vscc_config(struct vscc_config *cfg)
 {
 	memcpy(cfg, &spi_config, sizeof(*cfg));
 
diff --git a/src/mainboard/google/cyan/w25q64.c b/src/mainboard/google/cyan/w25q64.c
index 861a4645f8..5eea802942 100644
--- a/src/mainboard/google/cyan/w25q64.c
+++ b/src/mainboard/google/cyan/w25q64.c
@@ -18,52 +18,16 @@
 #include <string.h>
 
 /*
- * SPI lockdown configuration W25Q64FW.
+ * SPI VSCC configuration W25Q64FW.
  */
-#define SPI_OPMENU_0 0x01 /* WRSR: Write Status Register */
-#define SPI_OPTYPE_0 0x01 /* Write, no address */
-
-#define SPI_OPMENU_1 0x02 /* BYPR: Byte Program */
-#define SPI_OPTYPE_1 0x03 /* Write, address required */
-
-#define SPI_OPMENU_2 0x03 /* READ: Read Data */
-#define SPI_OPTYPE_2 0x02 /* Read, address required */
-
-#define SPI_OPMENU_3 0x05 /* RDSR: Read Status Register */
-#define SPI_OPTYPE_3 0x00 /* Read, no address */
-
-#define SPI_OPMENU_4 0x20 /* SE20: Sector Erase 0x20 */
-#define SPI_OPTYPE_4 0x03 /* Write, address required */
-
-#define SPI_OPMENU_5 0x9f /* RDID: Read ID */
-#define SPI_OPTYPE_5 0x00 /* Read, no address */
-
-#define SPI_OPMENU_6 0xd8 /* BED8: Block Erase 0xd8 */
-#define SPI_OPTYPE_6 0x03 /* Write, address required */
-
-#define SPI_OPMENU_7 0x0b /* FAST: Fast Read */
-#define SPI_OPTYPE_7 0x02 /* Read, address required */
-
-#define SPI_OPPREFIX ((0x50 << 8) | 0x06) /* EWSR and WREN */
-#define SPI_OPTYPE ((SPI_OPTYPE_7 << 14) | (SPI_OPTYPE_6 << 12) | \
-		    (SPI_OPTYPE_5 << 10) | (SPI_OPTYPE_4 <<  8) | \
-		    (SPI_OPTYPE_3 <<  6) | (SPI_OPTYPE_2 <<  4) | \
-		    (SPI_OPTYPE_1 <<  2) | (SPI_OPTYPE_0 <<  0))
-#define SPI_OPMENU_UPPER ((SPI_OPMENU_7 << 24) | (SPI_OPMENU_6 << 16) | \
-			  (SPI_OPMENU_5 <<  8) | (SPI_OPMENU_4 <<  0))
-#define SPI_OPMENU_LOWER ((SPI_OPMENU_3 << 24) | (SPI_OPMENU_2 << 16) | \
-			  (SPI_OPMENU_1 <<  8) | (SPI_OPMENU_0 <<  0))
 #define SPI_VSCC (WG_64_BYTE | EO(0x20) | BES_4_KB)
 
-static const struct spi_config spi_config = {
-	.preop = SPI_OPPREFIX,
-	.optype = SPI_OPTYPE,
-	.opmenu = { SPI_OPMENU_LOWER, SPI_OPMENU_UPPER },
+static const struct vscc_config spi_config = {
 	.lvscc =  SPI_VSCC,
 	.uvscc =  SPI_VSCC,
 };
 
-int mainboard_get_spi_config(struct spi_config *cfg)
+int mainboard_get_spi_vscc_config(struct vscc_config *cfg)
 {
 	memcpy(cfg, &spi_config, sizeof(*cfg));
 
diff --git a/src/mainboard/intel/strago/w25q64.c b/src/mainboard/intel/strago/w25q64.c
index 861a4645f8..5598de48a1 100644
--- a/src/mainboard/intel/strago/w25q64.c
+++ b/src/mainboard/intel/strago/w25q64.c
@@ -18,52 +18,17 @@
 #include <string.h>
 
 /*
- * SPI lockdown configuration W25Q64FW.
+ * SPI VSCC configuration W25Q64FW.
  */
-#define SPI_OPMENU_0 0x01 /* WRSR: Write Status Register */
-#define SPI_OPTYPE_0 0x01 /* Write, no address */
 
-#define SPI_OPMENU_1 0x02 /* BYPR: Byte Program */
-#define SPI_OPTYPE_1 0x03 /* Write, address required */
-
-#define SPI_OPMENU_2 0x03 /* READ: Read Data */
-#define SPI_OPTYPE_2 0x02 /* Read, address required */
-
-#define SPI_OPMENU_3 0x05 /* RDSR: Read Status Register */
-#define SPI_OPTYPE_3 0x00 /* Read, no address */
-
-#define SPI_OPMENU_4 0x20 /* SE20: Sector Erase 0x20 */
-#define SPI_OPTYPE_4 0x03 /* Write, address required */
-
-#define SPI_OPMENU_5 0x9f /* RDID: Read ID */
-#define SPI_OPTYPE_5 0x00 /* Read, no address */
-
-#define SPI_OPMENU_6 0xd8 /* BED8: Block Erase 0xd8 */
-#define SPI_OPTYPE_6 0x03 /* Write, address required */
-
-#define SPI_OPMENU_7 0x0b /* FAST: Fast Read */
-#define SPI_OPTYPE_7 0x02 /* Read, address required */
-
-#define SPI_OPPREFIX ((0x50 << 8) | 0x06) /* EWSR and WREN */
-#define SPI_OPTYPE ((SPI_OPTYPE_7 << 14) | (SPI_OPTYPE_6 << 12) | \
-		    (SPI_OPTYPE_5 << 10) | (SPI_OPTYPE_4 <<  8) | \
-		    (SPI_OPTYPE_3 <<  6) | (SPI_OPTYPE_2 <<  4) | \
-		    (SPI_OPTYPE_1 <<  2) | (SPI_OPTYPE_0 <<  0))
-#define SPI_OPMENU_UPPER ((SPI_OPMENU_7 << 24) | (SPI_OPMENU_6 << 16) | \
-			  (SPI_OPMENU_5 <<  8) | (SPI_OPMENU_4 <<  0))
-#define SPI_OPMENU_LOWER ((SPI_OPMENU_3 << 24) | (SPI_OPMENU_2 << 16) | \
-			  (SPI_OPMENU_1 <<  8) | (SPI_OPMENU_0 <<  0))
 #define SPI_VSCC (WG_64_BYTE | EO(0x20) | BES_4_KB)
 
-static const struct spi_config spi_config = {
-	.preop = SPI_OPPREFIX,
-	.optype = SPI_OPTYPE,
-	.opmenu = { SPI_OPMENU_LOWER, SPI_OPMENU_UPPER },
+static const struct vscc_config spi_config = {
 	.lvscc =  SPI_VSCC,
 	.uvscc =  SPI_VSCC,
 };
 
-int mainboard_get_spi_config(struct spi_config *cfg)
+int mainboard_get_spi_vscc_config(struct vscc_config *cfg)
 {
 	memcpy(cfg, &spi_config, sizeof(*cfg));
 
diff --git a/src/mainboard/portwell/m107/w25q64.c b/src/mainboard/portwell/m107/w25q64.c
index bc908f04b3..2f131f4ec6 100644
--- a/src/mainboard/portwell/m107/w25q64.c
+++ b/src/mainboard/portwell/m107/w25q64.c
@@ -20,57 +20,16 @@
 #include <drivers/spi/spi_winbond.h>
 
 /*
- * SPI lockdown configuration
+ * SPI VSCC configuration
  */
-#define SPI_OPMENU_0	CMD_W25_WRSR		/* Write Status Register */
-#define SPI_OPTYPE_0	SPI_OPTYPE_WR_NOADDR	/* Write, no address */
-
-#define SPI_OPMENU_1	CMD_W25_PP		/* BYPR: Byte Program */
-#define SPI_OPTYPE_1	SPI_OPTYPE_WR_ADDR	/* Write, address required */
-
-#define SPI_OPMENU_2	CMD_W25_READ		/* Read Data */
-#define SPI_OPTYPE_2	SPI_OPTYPE_RD_ADDR	/* Read, address required */
-
-#define SPI_OPMENU_3	CMD_W25_RDSR		/* Read Status Register */
-#define SPI_OPTYPE_3	SPI_OPTYPE_RD_NOADDR	/* Read, no address */
-
-#define SPI_OPMENU_4	CMD_W25_SE		/* Sector Erase */
-#define SPI_OPTYPE_4	SPI_OPTYPE_WR_ADDR	/* Write, address required */
-
-#define SPI_OPMENU_5	CMD_W25_RDID		/* Read ID */
-#define SPI_OPTYPE_5	SPI_OPTYPE_RD_NOADDR	/* Read, no address */
-
-#define SPI_OPMENU_6	CMD_W25_BE		/* BE: Block Erase */
-#define SPI_OPTYPE_6	SPI_OPTYPE_WR_ADDR	/* Write, address required */
-
-#define SPI_OPMENU_7	CMD_W25_FAST_READ	/* FAST: Fast Read */
-#define SPI_OPTYPE_7	SPI_OPTYPE_RD_ADDR	/* Read, address required */
-
-#define SPI_OPPREFIX	CMD_W25_WREN		/* WREN only to be inline */
-						/* with flashrom */
-
-#define SPI_OPTYPE ((SPI_OPTYPE_7 << 14) | (SPI_OPTYPE_6 << 12) | \
-		    (SPI_OPTYPE_5 << 10) | (SPI_OPTYPE_4 <<  8) | \
-		    (SPI_OPTYPE_3 <<  6) | (SPI_OPTYPE_2 <<  4) | \
-		    (SPI_OPTYPE_1 <<  2) | (SPI_OPTYPE_0 <<  0))
-
-#define SPI_OPMENU_UPPER ((SPI_OPMENU_7 << 24) | (SPI_OPMENU_6 << 16) | \
-			  (SPI_OPMENU_5 <<  8) | (SPI_OPMENU_4 <<  0))
-
-#define SPI_OPMENU_LOWER ((SPI_OPMENU_3 << 24) | (SPI_OPMENU_2 << 16) | \
-			  (SPI_OPMENU_1 <<  8) | (SPI_OPMENU_0 <<  0))
-
 #define SPI_VSCC (WG_64_BYTE | EO(0x20) | BES_4_KB)
 
-static const struct spi_config spi_config = {
-	.preop = CMD_W25_WREN,
-	.optype = SPI_OPTYPE,
-	.opmenu = { SPI_OPMENU_LOWER, SPI_OPMENU_UPPER },
+static const struct vscc_config spi_config = {
 	.lvscc =  SPI_VSCC,
 	.uvscc =  SPI_VSCC,
 };
 
-int mainboard_get_spi_config(struct spi_config *cfg)
+int mainboard_get_spi_vscc_config(struct vscc_config *cfg)
 {
 	memcpy(cfg, &spi_config, sizeof(*cfg));
 
diff --git a/src/soc/intel/braswell/include/soc/spi.h b/src/soc/intel/braswell/include/soc/spi.h
index 47de9da55b..0234021e65 100644
--- a/src/soc/intel/braswell/include/soc/spi.h
+++ b/src/soc/intel/braswell/include/soc/spi.h
@@ -23,14 +23,6 @@
 /* These registers live behind SPI_BASE_ADDRESS. */
 #define HSFSTS				0x04
 # define FLOCKDN			(0x1 << 15)
-#define PREOP				0x94
-#define OPTYPE				0x96
-# define SPI_OPTYPE_RD_NOADDR		0x00	/* Read, no address */
-# define SPI_OPTYPE_WR_NOADDR		0x01	/* Write, no address */
-# define SPI_OPTYPE_RD_ADDR		0x02	/* Read, address required */
-# define SPI_OPTYPE_WR_ADDR		0x03	/* Write, address required */
-#define OPMENU0				0x98
-#define OPMENU1				0x9c
 #define LVSCC				0xc4
 # define VCL				(0x1 << 23)
 # define EO(x)				(((x) & 0xff) << 8)
@@ -53,17 +45,14 @@
 # define BCR_WPD			(0x1 << 0)
 
 /*
- * SPI lockdown configuration.
+ * SPI VSCC configuration.
  */
-struct spi_config {
-	uint16_t preop;
-	uint16_t optype;
-	uint32_t opmenu[2];
+struct vscc_config {
 	uint32_t lvscc;
 	uint32_t uvscc;
 };
 
 /* Return 0 on success < 0 on failure. */
-int mainboard_get_spi_config(struct spi_config *cfg);
+int mainboard_get_spi_vscc_config(struct vscc_config *cfg);
 
 #endif /* _SOC_SPI_H_ */
diff --git a/src/soc/intel/braswell/southcluster.c b/src/soc/intel/braswell/southcluster.c
index c233dc8172..8b13fd0e82 100644
--- a/src/soc/intel/braswell/southcluster.c
+++ b/src/soc/intel/braswell/southcluster.c
@@ -42,6 +42,7 @@
 #include <soc/spi.h>
 #include <spi-generic.h>
 #include <stdint.h>
+#include <southbridge/intel/common/spi.h>
 
 static void sc_set_serial_irqs_mode(struct device *dev, enum serirq_mode mode)
 {
@@ -608,13 +609,6 @@ static const struct pci_driver southcluster __pci_driver = {
 	.device		= LPC_DEVID,
 };
 
-int __weak mainboard_get_spi_config(struct spi_config *cfg)
-{
-	printk(BIOS_SPEW, "%s/%s (0x%p)\n",
-			__FILE__, __func__, (void *)cfg);
-	return -1;
-}
-
 static void finalize_chipset(void *unused)
 {
 	void *bcr = (void *)(SPI_BASE_ADDRESS + BCR);
@@ -622,7 +616,7 @@ static void finalize_chipset(void *unused)
 	void *gen_pmcon2 = (void *)(PMC_BASE_ADDRESS + GEN_PMCON2);
 	void *etr = (void *)(PMC_BASE_ADDRESS + ETR);
 	uint8_t *spi = (uint8_t *)SPI_BASE_ADDRESS;
-	struct spi_config cfg;
+	struct vscc_config cfg;
 
 	printk(BIOS_SPEW, "%s/%s (0x%p)\n",
 			__FILE__, __func__, unused);
@@ -639,14 +633,12 @@ static void finalize_chipset(void *unused)
 	/*  Set the CF9 lock. */
 	write32(etr, read32(etr) | CF9LOCK);
 
-	if (mainboard_get_spi_config(&cfg) < 0) {
-		printk(BIOS_DEBUG, "No SPI lockdown configuration.\n");
+	spi_finalize_ops();
+	write16(spi + HSFSTS, read16(spi + HSFSTS) | FLOCKDN);
+
+	if (mainboard_get_spi_vscc_config(&cfg) < 0) {
+		printk(BIOS_DEBUG, "No SPI VSCC configuration.\n");
 	} else {
-		write16(spi + PREOP, cfg.preop);
-		write16(spi + OPTYPE, cfg.optype);
-		write32(spi + OPMENU0, cfg.opmenu[0]);
-		write32(spi + OPMENU1, cfg.opmenu[1]);
-		write16(spi + HSFSTS, read16(spi + HSFSTS) | FLOCKDN);
 		write32(spi + UVSCC, cfg.uvscc);
 		write32(spi + LVSCC, cfg.lvscc | VCL);
 	}