diff options
| author | Marshall Dawson <marshalldawson3rd@gmail.com> | 2018-09-27 08:12:38 -0600 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2018-09-28 20:12:45 +0000 |
| commit | 61452a11e23c00c978e182af4ad1e6d958fb6db2 (patch) | |
| tree | b042f12fb0369d0c08ab195881b744192b4839f2 /src | |
| parent | 6fe2937770f3d32fce63bea41869e356b51e1473 (diff) | |
amd/stoneyridge: Make gnvs ASL whitespace consistent
The globalnvs.asl file had become mixed with tabs and spaces to align
columns. Use all tabs to align the comments.
BUG=b:BUG=b:77602074
Change-Id: Ife4cf86372a8e24e78b38cca0254dd9fa00dd6b0
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/28764
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src')
| -rw-r--r-- | src/soc/amd/stoneyridge/acpi/globalnvs.asl | 26 |
1 files changed, 13 insertions, 13 deletions
diff --git a/src/soc/amd/stoneyridge/acpi/globalnvs.asl b/src/soc/amd/stoneyridge/acpi/globalnvs.asl index 7e696aa816..ba50e3874d 100644 --- a/src/soc/amd/stoneyridge/acpi/globalnvs.asl +++ b/src/soc/amd/stoneyridge/acpi/globalnvs.asl @@ -28,19 +28,19 @@ Field (GNVS, ByteAcc, NoLock, Preserve) { /* Miscellaneous */ Offset (0x00), - PCNT, 8, // 0x00 - Processor Count - PPCM, 8, // 0x01 - Max PPC State - LIDS, 8, // 0x02 - LID State - PWRS, 8, // 0x03 - AC Power State - DPTE, 8, // 0x04 - Enable DPTF - CBMC, 32, // 0x05 - 0x08 - coreboot Memory Console - PM1I, 64, // 0x09 - 0x10 - System Wake Source - PM1 Index - GPEI, 64, // 0x11 - 0x18 - GPE Wake Source - NHLA, 64, // 0x19 - 0x20 - NHLT Address - NHLL, 32, // 0x21 - 0x24 - NHLT Length - PRT0, 32, // 0x25 - 0x28 - PERST_0 Address - SCDP, 8, // 0x29 - SD_CD GPIO portid - SCDO, 8, // 0x2A - GPIO pad offset relative to the community + PCNT, 8, // 0x00 - Processor Count + PPCM, 8, // 0x01 - Max PPC State + LIDS, 8, // 0x02 - LID State + PWRS, 8, // 0x03 - AC Power State + DPTE, 8, // 0x04 - Enable DPTF + CBMC, 32, // 0x05 - 0x08 - coreboot Memory Console + PM1I, 64, // 0x09 - 0x10 - System Wake Source - PM1 Index + GPEI, 64, // 0x11 - 0x18 - GPE Wake Source + NHLA, 64, // 0x19 - 0x20 - NHLT Address + NHLL, 32, // 0x21 - 0x24 - NHLT Length + PRT0, 32, // 0x25 - 0x28 - PERST_0 Address + SCDP, 8, // 0x29 - SD_CD GPIO portid + SCDO, 8, // 0x2A - GPIO pad offset relative to the community TMPS, 8, // 0x2B - Temperature Sensor ID TLVL, 8, // 0x2C - Throttle Level Limit FLVL, 8, // 0x2D - Current FAN Level |