diff options
| author | Subrata Banik <subratabanik@google.com> | 2022-12-13 14:10:48 +0530 |
|---|---|---|
| committer | Subrata Banik <subratabanik@google.com> | 2022-12-15 08:11:30 +0000 |
| commit | 5dfec718290609dc0fd0331070ad703107e0b7e7 (patch) | |
| tree | f0190e070476d72bef9ff7500feab5cd34ff2004 /src | |
| parent | 0f15030700ae0c9a4102b3f3d6551a1a7e502c14 (diff) | |
soc/intel/{adl, cmn/pcie}: Fix ASPM configuration enum definitions
As per PCI Express Base Specification 5.0 section 5.4.1.3 ASPM
Configuration
+-----------------------+-------------------------------+
| Field Description | ASPM Support |
+-----------------------+-------------------------------+
| 00b | No ASPM support |
+-----------------------+-------------------------------+
| 01b | L0s Supported |
+-----------------------+-------------------------------+
| 10b | L1 Supported |
+-----------------------+-------------------------------+
| 11b | L0s and L1 Supported |
+-----------------------+-------------------------------+
100b aka 0x4 is added by FSP to allow auto configuration (to avoid
conflicting with the PCI specification defined values).
Additionally, changed enum definition which is now meeting the FSP expectations better.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I8c9055f721e144f2ff5055e5f99ea641efc4d268
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70719
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src')
| -rw-r--r-- | src/soc/intel/alderlake/fsp_params.c | 19 | ||||
| -rw-r--r-- | src/soc/intel/common/block/include/intelblocks/pcie_rp.h | 1 |
2 files changed, 7 insertions, 13 deletions
diff --git a/src/soc/intel/alderlake/fsp_params.c b/src/soc/intel/alderlake/fsp_params.c index 224cf8a9ea..3463c9f923 100644 --- a/src/soc/intel/alderlake/fsp_params.c +++ b/src/soc/intel/alderlake/fsp_params.c @@ -479,23 +479,18 @@ static int get_l1_substate_control(enum L1_substates_control ctl) } /* - * Chip config parameter pcie_rp_aspm uses (UPD value + 1) because - * a UPD value of 0 for pcie_rp_aspm means disabled. In order to ensure - * that the mainboard setting does not disable ASPM incorrectly, chip - * config parameter values are offset by 1 with 0 meaning use FSP UPD default. * get_aspm_control() ensures that the right UPD value is set in fsp_params. - * 0: Use FSP UPD default - * 1: Disable ASPM - * 2: L0s only - * 3: L1 only - * 4: L0s and L1 - * 5: Auto configuration + * 0: Disable ASPM + * 1: L0s only + * 2: L1 only + * 3: L0s and L1 + * 4: Auto configuration */ static unsigned int get_aspm_control(enum ASPM_control ctl) { - if ((ctl > ASPM_AUTO) || (ctl == ASPM_DEFAULT)) + if (ctl > ASPM_AUTO) ctl = ASPM_AUTO; - return ctl - 1; + return ctl; } /* This function returns the VccIn Aux Imon IccMax values for ADL and RPL diff --git a/src/soc/intel/common/block/include/intelblocks/pcie_rp.h b/src/soc/intel/common/block/include/intelblocks/pcie_rp.h index 9832feb83f..a4e350055e 100644 --- a/src/soc/intel/common/block/include/intelblocks/pcie_rp.h +++ b/src/soc/intel/common/block/include/intelblocks/pcie_rp.h @@ -46,7 +46,6 @@ enum L1_substates_control { /* This enum is for passing into an FSP UPD, typically ASPM */ enum ASPM_control { - ASPM_DEFAULT, ASPM_DISABLE, ASPM_L0S, ASPM_L1, |