diff options
| author | Kevin Chiu <kevin.chiu.17802@gmail.com> | 2021-01-22 14:33:32 +0800 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2021-01-25 08:51:21 +0000 |
| commit | 5a27b756423b5913c32ffbfccc9014c60b20e910 (patch) | |
| tree | e42170d6dec83073b93d69dd6eec34c2303e3da1 /src | |
| parent | cbde6410a039b37d0df07e53953baad552bd22cc (diff) | |
mb/google/zork: update USB 2.0 controller Lane Parameter for dirinboz
From AMD USB phy specialist recommended that for DB port2 (type-A), port3 (type-C C1)
the most effective corrections for the depressed eye are:
tx_rise_tune=0x0
tx_pre_emp_amp_tune=0x3
tx_fsls_tune = 0x3
BUG=b:165209698
BRANCH=zork
TEST=1. emerge-zork coreboot
2. pass USB 2.0 SI eye diagram verification
Change-Id: I80afd6bf1257b9a72d0d7651b48d243ebaf5de2f
Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49824
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Rob Barnes <robbarnes@google.com>
Diffstat (limited to 'src')
| -rw-r--r-- | src/mainboard/google/zork/variants/dirinboz/overridetree.cb | 10 |
1 files changed, 5 insertions, 5 deletions
diff --git a/src/mainboard/google/zork/variants/dirinboz/overridetree.cb b/src/mainboard/google/zork/variants/dirinboz/overridetree.cb index 6416a5c807..554cdeac94 100644 --- a/src/mainboard/google/zork/variants/dirinboz/overridetree.cb +++ b/src/mainboard/google/zork/variants/dirinboz/overridetree.cb @@ -21,7 +21,7 @@ chip soc/amd/picasso register "telemetry_vddcr_soc_offset" = "167" # End : OPN Performance Configuration - # USB 2.0 strength + # USB 2.0 strength - MB type-C C0 register "usb_2_port_tune_params[0]" = "{ .com_pds_tune = 0x07, .sq_rx_tune = 0x3, @@ -34,27 +34,27 @@ chip soc/amd/picasso .tx_res_tune = 0x01, }" - # USB 2.0 strength + # USB 2.0 strength - DB type-A register "usb_2_port_tune_params[2]" = "{ .com_pds_tune = 0x07, .sq_rx_tune = 0x3, .tx_fsls_tune = 0x3, .tx_pre_emp_amp_tune = 0x03, .tx_pre_emp_pulse_tune = 0x0, - .tx_rise_tune = 0x1, + .tx_rise_tune = 0x0, .tx_vref_tune = 0xe, .tx_hsxv_tune = 0x3, .tx_res_tune = 0x01, }" - # USB 2.0 strength + # USB 2.0 strength - DB type-C C1 register "usb_2_port_tune_params[3]" = "{ .com_pds_tune = 0x07, .sq_rx_tune = 0x3, .tx_fsls_tune = 0x3, .tx_pre_emp_amp_tune = 0x03, .tx_pre_emp_pulse_tune = 0x0, - .tx_rise_tune = 0x1, + .tx_rise_tune = 0x0, .tx_vref_tune = 0xe, .tx_hsxv_tune = 0x3, .tx_res_tune = 0x01, |