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authorPhilipp Deppenwiese <zaolin@das-labor.org>2019-09-20 10:41:23 -0700
committerPatrick Georgi <pgeorgi@google.com>2019-09-22 20:12:54 +0000
commit58d668c387160b15cb059708e71b67ceb7ff6db4 (patch)
tree8cb02bd423d6827eb313a33c3ddf7cd7b6b59d85 /src
parent31f5283563148fd7b22d0c1db6d58a053398fe94 (diff)
mb/ocp/monolake: Add vboot RO only support
Change-Id: I28a21d64e2781af294670a94c1fc88fb81e80f9e Signed-off-by: Philipp Deppenwiese <zaolin@das-labor.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35492 Reviewed-by: Andrey Petrov <anpetrov@fb.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src')
-rw-r--r--src/mainboard/ocp/monolake/Kconfig8
-rw-r--r--src/mainboard/ocp/monolake/cmos.layout1
-rw-r--r--src/mainboard/ocp/monolake/vboot-ro.fmd22
3 files changed, 31 insertions, 0 deletions
diff --git a/src/mainboard/ocp/monolake/Kconfig b/src/mainboard/ocp/monolake/Kconfig
index 9536c30203..ad4e9c7208 100644
--- a/src/mainboard/ocp/monolake/Kconfig
+++ b/src/mainboard/ocp/monolake/Kconfig
@@ -14,6 +14,14 @@ config BOARD_SPECIFIC_OPTIONS
select MAINBOARD_HAS_TPM1
select IPMI_KCS
+config VBOOT
+ select VBOOT_VBNV_CMOS
+ select VBOOT_NO_BOARD_SUPPORT
+ select GBB_FLAG_DISABLE_LID_SHUTDOWN
+ select GBB_FLAG_DISABLE_PD_SOFTWARE_SYNC
+ select GBB_FLAG_DISABLE_EC_SOFTWARE_SYNC
+ select GBB_FLAG_DISABLE_FWMP
+
config INTEGRATED_UART
def_bool n
diff --git a/src/mainboard/ocp/monolake/cmos.layout b/src/mainboard/ocp/monolake/cmos.layout
index 3c5bc3b03d..3aaa56b569 100644
--- a/src/mainboard/ocp/monolake/cmos.layout
+++ b/src/mainboard/ocp/monolake/cmos.layout
@@ -81,6 +81,7 @@ entries
408 1 e 1 nmi
409 2 e 7 power_on_after_fail
#411 5 r 0 unused
+416 128 r 0 vbnv
# MRC Scrambler Seed values
896 32 r 0 mrc_scrambler_seed
diff --git a/src/mainboard/ocp/monolake/vboot-ro.fmd b/src/mainboard/ocp/monolake/vboot-ro.fmd
new file mode 100644
index 0000000000..44be3370ce
--- /dev/null
+++ b/src/mainboard/ocp/monolake/vboot-ro.fmd
@@ -0,0 +1,22 @@
+FLASH 16M {
+ SI_ALL@0x0 0x800000 {
+ SI_DESC@0x0 0x1000
+ SI_ME@0x1000 0x7ff000
+ }
+ SI_BIOS@0x800000 0x800000 {
+ MISC_RW@0x0 0x20000 {
+ RW_MRC_CACHE@0x0 0x10000
+ RW_VPD(PRESERVE)@0x010000 0x4000
+ }
+ WP_RO@0x020000 0x7e0000 {
+ RO_VPD(PRESERVE)@0x0 0x4000
+ RO_SECTION@0x4000 0x7dc000 {
+ FMAP@0x0 0x800
+ RO_FRID@0x800 0x40
+ RO_FRID_PAD@0x840 0x7c0
+ GBB@0x1000 0x4000
+ COREBOOT(CBFS)@0x5000 0x7d7000
+ }
+ }
+ }
+}