diff options
| author | Subrata Banik <subratabanik@google.com> | 2023-01-16 16:07:32 +0530 |
|---|---|---|
| committer | Subrata Banik <subratabanik@google.com> | 2023-01-18 11:50:11 +0000 |
| commit | 55546699f17a30bca0f6bf260eee69aa30da5ede (patch) | |
| tree | 2b598e972df77b5611d49131721d5124acead724 /src | |
| parent | b03d6f15b48468c6f3a5da45df6204eb43db6eaa (diff) | |
soc/intel/alderlake: Fix incorrect `prev_sleep_state` issue
The patch fixes indication of incorrect `prev_sleep_state` on the next
boot after global reset trigger. The existing code misses an important check about `if PCH doesn't set the WAK_STS` while checking power
failure. As a result, every early warm/global reset is considered
as power failure after looking into the PMC MMIO CON-A register
alone (as ignoring the ACPI PM_CTRL.WAK_STS bit).
As per the code comment this code logic is expected to check the power
failure reason if PCH doesn't set the WAK_STS while waking from G3
state.
TEST=Able to build and boot google/taeko.
Without this patch:
Observation: Resuming after a warm reset is considered as
`prev_sleep_state 5` although the SLP_TYP is zero and WAK_STS bit
is set.
pm1_sts: 8100 pm1_en: 0000 pm1_cnt: 00000000
GEN_PMCON: d1215238 00002200
....
prev_sleep_state 5
With this patch:
Observation: Resuming after a warm reset is considered as
`prev_sleep_state 0`. It matches with the SLP_TYP is zero and
WAK_STS bit is set.
pm1_sts: 8100 pm1_en: 0000 pm1_cnt: 00000000
GEN_PMCON: d1215238 00002200
....
prev_sleep_state 0
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I52f9c261f4eea34e6d2300c8de97ee018d886189
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71987
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src')
| -rw-r--r-- | src/soc/intel/alderlake/pmutil.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/soc/intel/alderlake/pmutil.c b/src/soc/intel/alderlake/pmutil.c index cba3ff43a2..3e9f71f78d 100644 --- a/src/soc/intel/alderlake/pmutil.c +++ b/src/soc/intel/alderlake/pmutil.c @@ -202,7 +202,7 @@ int soc_prev_sleep_state(const struct chipset_power_state *ps, int prev_sleep_st * S5 because the PCH does not set the WAK_STS bit when waking * from a true G3 state. */ - if (ps->gen_pmcon_a & (PWR_FLR | SUS_PWR_FLR)) + if (!(ps->pm1_sts & WAK_STS) && (ps->gen_pmcon_a & (PWR_FLR | SUS_PWR_FLR))) prev_sleep_state = ACPI_S5; /* |