diff options
| author | Arthur Heymans <arthur@aheymans.xyz> | 2019-11-01 21:53:36 +0100 |
|---|---|---|
| committer | Nico Huber <nico.h@gmx.de> | 2019-11-10 11:46:10 +0000 |
| commit | 55069d15d8a6dcd7f8eaaf36e85e5d7a53fdaae6 (patch) | |
| tree | 3ce7924b9a242256086daf771e6b2f7327cf9df5 /src | |
| parent | 7f22933e98ec70b31b939b2ab70d6b8715640848 (diff) | |
arch/riscv: Pass cbmem_top to ramstage via calling argument
Tested on the Qemu-Virt target both 32 and 64 bit.
Change-Id: I5c74cd5d3ee292931c5bbd2e4075f88381429f72
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36558
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src')
| -rw-r--r-- | src/arch/riscv/Kconfig | 1 | ||||
| -rw-r--r-- | src/arch/riscv/boot.c | 9 | ||||
| -rw-r--r-- | src/arch/riscv/ramstage.S | 7 |
3 files changed, 11 insertions, 6 deletions
diff --git a/src/arch/riscv/Kconfig b/src/arch/riscv/Kconfig index f2ca571c97..9ee781b4f0 100644 --- a/src/arch/riscv/Kconfig +++ b/src/arch/riscv/Kconfig @@ -90,6 +90,7 @@ config ARCH_ROMSTAGE_RISCV config ARCH_RAMSTAGE_RISCV bool default n + select RAMSTAGE_CBMEM_TOP_ARG config RISCV_USE_ARCH_TIMER bool diff --git a/src/arch/riscv/boot.c b/src/arch/riscv/boot.c index d3ae693376..aaaac485ea 100644 --- a/src/arch/riscv/boot.c +++ b/src/arch/riscv/boot.c @@ -36,7 +36,7 @@ struct arch_prog_run_args { static void do_arch_prog_run(struct arch_prog_run_args *args) { - int hart_id; + int hart_id = HLS()->hart_id; struct prog *prog = args->prog; void *fdt = HLS()->fdt; @@ -49,11 +49,8 @@ static void do_arch_prog_run(struct arch_prog_run_args *args) else run_payload(prog, fdt, RISCV_PAYLOAD_MODE_S); } else { - void (*doit)(int hart_id, void *fdt) = prog_entry(prog); - - hart_id = HLS()->hart_id; - - doit(hart_id, fdt); + void (*doit)(int hart_id, void *fdt, void *arg) = prog_entry(prog); + doit(hart_id, fdt, prog_entry_arg(prog)); } die("Failed to run stage"); diff --git a/src/arch/riscv/ramstage.S b/src/arch/riscv/ramstage.S index 28183e50e0..2468c231bc 100644 --- a/src/arch/riscv/ramstage.S +++ b/src/arch/riscv/ramstage.S @@ -20,6 +20,13 @@ .section ".text._start", "ax", %progbits .globl _start _start: + /* cbmem_top is passed via a2 */ + la t0, _cbmem_top_ptr +#if __riscv_xlen == 32 + sw a2, (t0) +#elif __riscv_xlen == 64 + sd a2, (t0) +#endif # initialize stack point for each hart # and the stack must be page-aligned. # 0xDEADBEEF used to check stack overflow |