diff options
| author | David Hendricks <dhendrix@chromium.org> | 2013-01-02 17:41:51 -0800 |
|---|---|---|
| committer | Ronald G. Minnich <rminnich@gmail.com> | 2013-01-03 06:46:09 +0100 |
| commit | 4c2245eb67b0eabf18fc9b6788bc05d962ef5e0e (patch) | |
| tree | 947eed2f66e86585ec5eb88313b389a539ce6a5d /src | |
| parent | 454856b274ed81babdcea4b4ed5fb922fe0caf89 (diff) | |
snow: Stuff to support building image with BL1
This patch does two things which will take effect in follow-up
patches:
1. Add an intermediate Makefile rule for dd'ing BL1 into the
coreboot.rom pre-image. This is modeled after a similar hack
for the bd82x6x southbridge.
2. Add a Kconfig variable, BOOTBLOCK_OFFSET, which will be used to
pass the bootblock offset into cbfstool.
Change-Id: I89da255dc903c387b754b06a11bb3439035ead87
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: http://review.coreboot.org/2093
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Diffstat (limited to 'src')
| -rw-r--r-- | src/cpu/samsung/exynos5250/Kconfig | 7 | ||||
| -rw-r--r-- | src/cpu/samsung/exynos5250/Makefile.inc | 10 |
2 files changed, 17 insertions, 0 deletions
diff --git a/src/cpu/samsung/exynos5250/Kconfig b/src/cpu/samsung/exynos5250/Kconfig index c2d9b9fddc..360c57f878 100644 --- a/src/cpu/samsung/exynos5250/Kconfig +++ b/src/cpu/samsung/exynos5250/Kconfig @@ -1,3 +1,10 @@ +config BOOTBLOCK_OFFSET + hex "Bootblock offset" + default 0x3400 + help + This is where the Coreboot bootblock resides. For Exynos5250, + this value is pre-determined by the vendor-provided BL1. + config EXYNOS_ACE_SHA bool default n diff --git a/src/cpu/samsung/exynos5250/Makefile.inc b/src/cpu/samsung/exynos5250/Makefile.inc index 556631a25a..1ff232780a 100644 --- a/src/cpu/samsung/exynos5250/Makefile.inc +++ b/src/cpu/samsung/exynos5250/Makefile.inc @@ -1,3 +1,8 @@ +# Run an intermediate step when producing coreboot.rom +# that adds additional components to the final firmware +# image outside of CBFS +INTERMEDIATE += exynos5250_add_bl1 + romstage-y += clock.c romstage-y += clock_init.c romstage-y += exynos_cache.c @@ -30,3 +35,8 @@ ramstage-y += uart.c ramstage-$(CONFIG_SPL_BUILD) += lowlevel_init_c.c ramstage-$(CONFIG_SPL_BUILD) += dmc_common.c ramstage-$(CONFIG_SPL_BUILD) += dmc_init_ddr3.c + +exynos5250_add_bl1: $(obj)/coreboot.pre + printf " DD Adding Samsung Exynos5250 BL1\n" + dd if=3rdparty/cpu/samsung/exynos5250/E5250.nbl1.bin \ + of=$(obj)/coreboot.pre conv=notrunc >/dev/null 2>&1 |