broadwell: Factor out PIRQ routing from devicetree

All boards disable PIRQs, except purism/librem_bdw. Since IRQ0 is
invalid and modern OSes don't use PIRQ routing, disable the PIRQs.

Change-Id: I93b074474c3c6d4329903cab928dc41e1d3a3fb3
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43868
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>

5 files changed, 11 insertions, 56 deletions

diff --git a/src/mainboard/google/auron/devicetree.cb b/src/mainboard/google/auron/devicetree.cb
index 65d4ce9c47..a3097624fe 100644
--- a/src/mainboard/google/auron/devicetree.cb
+++ b/src/mainboard/google/auron/devicetree.cb
@@ -15,15 +15,6 @@ chip soc/intel/broadwell
 	# Set backlight PWM value for eDP
 	register "gpu_pch_backlight_pwm_hz" = "200"
 
-	register "pirqa_routing" = "0x80"
-	register "pirqb_routing" = "0x80"
-	register "pirqc_routing" = "0x80"
-	register "pirqd_routing" = "0x80"
-	register "pirqe_routing" = "0x80"
-	register "pirqf_routing" = "0x80"
-	register "pirqg_routing" = "0x80"
-	register "pirqh_routing" = "0x80"
-
 	# EC range is 0x800-0x9ff
 	register "gen1_dec" = "0x00fc0801"
 	register "gen2_dec" = "0x00fc0901"
diff --git a/src/mainboard/google/jecht/devicetree.cb b/src/mainboard/google/jecht/devicetree.cb
index 4856cca65a..c4707e0c00 100644
--- a/src/mainboard/google/jecht/devicetree.cb
+++ b/src/mainboard/google/jecht/devicetree.cb
@@ -9,15 +9,6 @@ chip soc/intel/broadwell
 	# Enable HDMI Hotplug with 6ms pulse
 	register "gpu_dp_b_hotplug" = "0x06"
 
-	register "pirqa_routing" = "0x80"
-	register "pirqb_routing" = "0x80"
-	register "pirqc_routing" = "0x80"
-	register "pirqd_routing" = "0x80"
-	register "pirqe_routing" = "0x80"
-	register "pirqf_routing" = "0x80"
-	register "pirqg_routing" = "0x80"
-	register "pirqh_routing" = "0x80"
-
 	# SuperIO range is 0x700-0x73f
 	register "gen2_dec" = "0x003c0701"
 
diff --git a/src/mainboard/intel/wtm2/devicetree.cb b/src/mainboard/intel/wtm2/devicetree.cb
index 88c033ea4d..bff39b72eb 100644
--- a/src/mainboard/intel/wtm2/devicetree.cb
+++ b/src/mainboard/intel/wtm2/devicetree.cb
@@ -9,15 +9,6 @@ chip soc/intel/broadwell
 	# Enable DVI Hotplug with 6ms pulse
 	register "gpu_dp_b_hotplug" = "0x06"
 
-	register "pirqa_routing" = "0x80"
-	register "pirqb_routing" = "0x80"
-	register "pirqc_routing" = "0x80"
-	register "pirqd_routing" = "0x80"
-	register "pirqe_routing" = "0x80"
-	register "pirqf_routing" = "0x80"
-	register "pirqg_routing" = "0x80"
-	register "pirqh_routing" = "0x80"
-
 	register "alt_gp_smi_en" = "0x0000"
 	register "gpe0_en_1" = "0x00000400"
 	register "gpe0_en_2" = "0x00000000"
diff --git a/src/soc/intel/broadwell/chip.h b/src/soc/intel/broadwell/chip.h
index 45f91d8aef..554399823a 100644
--- a/src/soc/intel/broadwell/chip.h
+++ b/src/soc/intel/broadwell/chip.h
@@ -8,19 +8,6 @@
 #include <stdint.h>
 
 struct soc_intel_broadwell_config {
-	/*
-	 * Interrupt Routing configuration
-	 * If bit7 is 1, the interrupt is disabled.
-	 */
-	uint8_t pirqa_routing;
-	uint8_t pirqb_routing;
-	uint8_t pirqc_routing;
-	uint8_t pirqd_routing;
-	uint8_t pirqe_routing;
-	uint8_t pirqf_routing;
-	uint8_t pirqg_routing;
-	uint8_t pirqh_routing;
-
 	/* GPE configuration */
 	uint32_t gpe0_en_1;
 	uint32_t gpe0_en_2;
diff --git a/src/soc/intel/broadwell/lpc.c b/src/soc/intel/broadwell/lpc.c
index 58cd35d1f6..b3f4fe5b2a 100644
--- a/src/soc/intel/broadwell/lpc.c
+++ b/src/soc/intel/broadwell/lpc.c
@@ -90,17 +90,18 @@ static void enable_hpet(struct device *dev)
 static void pch_pirq_init(struct device *dev)
 {
 	struct device *irq_dev;
-	config_t *config = config_of(dev);
 
-	pci_write_config8(dev, PIRQA_ROUT, config->pirqa_routing);
-	pci_write_config8(dev, PIRQB_ROUT, config->pirqb_routing);
-	pci_write_config8(dev, PIRQC_ROUT, config->pirqc_routing);
-	pci_write_config8(dev, PIRQD_ROUT, config->pirqd_routing);
+	const uint8_t pirq = 0x80;
+
+	pci_write_config8(dev, PIRQA_ROUT, pirq);
+	pci_write_config8(dev, PIRQB_ROUT, pirq);
+	pci_write_config8(dev, PIRQC_ROUT, pirq);
+	pci_write_config8(dev, PIRQD_ROUT, pirq);
 
-	pci_write_config8(dev, PIRQE_ROUT, config->pirqe_routing);
-	pci_write_config8(dev, PIRQF_ROUT, config->pirqf_routing);
-	pci_write_config8(dev, PIRQG_ROUT, config->pirqg_routing);
-	pci_write_config8(dev, PIRQH_ROUT, config->pirqh_routing);
+	pci_write_config8(dev, PIRQE_ROUT, pirq);
+	pci_write_config8(dev, PIRQF_ROUT, pirq);
+	pci_write_config8(dev, PIRQG_ROUT, pirq);
+	pci_write_config8(dev, PIRQH_ROUT, pirq);
 
 	for (irq_dev = all_devices; irq_dev; irq_dev = irq_dev->next) {
 		u8 int_pin = 0, int_line = 0;
@@ -112,16 +113,10 @@ static void pch_pirq_init(struct device *dev)
 
 		switch (int_pin) {
 		case 1: /* INTA# */
-			int_line = config->pirqa_routing;
-			break;
 		case 2: /* INTB# */
-			int_line = config->pirqb_routing;
-			break;
 		case 3: /* INTC# */
-			int_line = config->pirqc_routing;
-			break;
 		case 4: /* INTD# */
-			int_line = config->pirqd_routing;
+			int_line = pirq;
 			break;
 		}