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authorHannah Williams <hannah.williams@intel.com>2016-03-28 14:45:59 -0700
committerMartin Roth <martinroth@google.com>2016-05-26 17:23:01 +0200
commit483004f6d78767cf97c383d491e5ddc43818256f (patch)
tree21c7cfd12cce80c858e9a411499822abc6d8c8de /src
parent15a53c632991bd3cb202051f58eed465068663da (diff)
soc/apollolake: Add ish_enable in soc_intel_apollolake_config
Also initialize IshEnable in Silicon Init UPD with the value from devicetree.cb Signed-off-by: Hannah Williams <hannah.williams@intel.com> Change-Id: I8f57a7353471cc3efa21c7011cdd0b369d25275d Reviewed-on: https://review.coreboot.org/14894 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Diffstat (limited to 'src')
-rw-r--r--src/soc/intel/apollolake/chip.c2
-rw-r--r--src/soc/intel/apollolake/chip.h3
2 files changed, 5 insertions, 0 deletions
diff --git a/src/soc/intel/apollolake/chip.c b/src/soc/intel/apollolake/chip.c
index f56e1f22ea..610faa8273 100644
--- a/src/soc/intel/apollolake/chip.c
+++ b/src/soc/intel/apollolake/chip.c
@@ -120,6 +120,8 @@ void platform_fsp_silicon_init_params_cb(struct FSPS_UPD *silupd)
/* First 4k in BAR0 is used for IPC, real registers start at 4k offset */
silconfig->PmcBase = PMC_BAR0 + 0x1000;
silconfig->P2sbBase = P2SB_BAR;
+
+ silconfig->IshEnable = cfg->integrated_sensor_hub_enable;
}
struct chip_operations soc_intel_apollolake_ops = {
diff --git a/src/soc/intel/apollolake/chip.h b/src/soc/intel/apollolake/chip.h
index d74084ebff..3d9f5bd2d7 100644
--- a/src/soc/intel/apollolake/chip.h
+++ b/src/soc/intel/apollolake/chip.h
@@ -42,6 +42,9 @@ struct soc_intel_apollolake_config {
/* Configure serial IRQ (SERIRQ) line. */
enum serirq_mode serirq_mode;
+
+ /* Integrated Sensor Hub */
+ uint8_t integrated_sensor_hub_enable;
};
#endif /* _SOC_APOLLOLAKE_CHIP_H_ */