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authorSunway <lisunwei@huaqin.corp-partner.google.com>2021-03-29 15:20:13 +0800
committerPatrick Georgi <pgeorgi@google.com>2021-04-06 07:02:57 +0000
commit479247a5ecc0dbb234669a7d85ece9bd982aeb6b (patch)
tree7db463b1e21d79a473bc473d33cf625f0a8c9830 /src
parent68dc369a1cd1a9a58a8c18efb962444af4e31d7f (diff)
mb/google/kukui: katsu: update the EDID and initial code
The EDID and initial code are provided by STA (the vendor). BUG=b:183969078 TEST=Boots on Chromebook Katsu and displayed developer firmware screen successfully. Signed-off-by: Sunway <lisunwei@huaqin.corp-partner.google.com> Change-Id: I54e72c072b47d2be264ed7f0700812a6c704a104 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51918 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src')
-rw-r--r--src/mainboard/google/kukui/panel_params/panel-STA_2081101QFH032011_53G.c7
1 files changed, 4 insertions, 3 deletions
diff --git a/src/mainboard/google/kukui/panel_params/panel-STA_2081101QFH032011_53G.c b/src/mainboard/google/kukui/panel_params/panel-STA_2081101QFH032011_53G.c
index baf3dacc74..18e3cb7480 100644
--- a/src/mainboard/google/kukui/panel_params/panel-STA_2081101QFH032011_53G.c
+++ b/src/mainboard/google/kukui/panel_params/panel-STA_2081101QFH032011_53G.c
@@ -9,7 +9,7 @@ struct panel_serializable_data STA_QFH032011_53G = {
.panel_bits_per_color = 8,
.panel_bits_per_pixel = 24,
.mode = {
- .pixel_clock = 150451,
+ .pixel_clock = 165731,
.lvds_dual_channel = 0,
.refresh = 60,
.ha = 1200, .hbl = 210, .hso = 100, .hspw = 10,
@@ -20,7 +20,7 @@ struct panel_serializable_data STA_QFH032011_53G = {
},
.orientation = LB_FB_ORIENTATION_LEFT_UP,
.init = {
- INIT_DCS_CMD(0xB0, 0x41),
+ INIT_DCS_CMD(0xB0, 0x01),
INIT_DCS_CMD(0xC3, 0x4F),
INIT_DCS_CMD(0xC4, 0x40),
INIT_DCS_CMD(0xC5, 0x40),
@@ -63,13 +63,14 @@ struct panel_serializable_data STA_QFH032011_53G = {
INIT_DCS_CMD(0xD3, 0x04),
INIT_DCS_CMD(0xD4, 0x01),
INIT_DCS_CMD(0xD5, 0x00),
- INIT_DCS_CMD(0xC6, 0x03),
+ INIT_DCS_CMD(0xD6, 0x03),
INIT_DCS_CMD(0xD7, 0x04),
INIT_DCS_CMD(0xD9, 0x01),
INIT_DCS_CMD(0xDB, 0x01),
INIT_DCS_CMD(0xE4, 0xF0),
INIT_DCS_CMD(0xE5, 0x0A),
INIT_DCS_CMD(0xB0, 0x00),
+ INIT_DCS_CMD(0xCC, 0x08),
INIT_DCS_CMD(0xC2, 0x08),
INIT_DCS_CMD(0xC4, 0x10),
INIT_DCS_CMD(0xB0, 0x02),