diff options
author | Alexandru Gagniuc <mr.nuke.me@gmail.com> | 2015-02-18 14:51:41 -0600 |
---|---|---|
committer | Alexandru Gagniuc <mr.nuke.me@gmail.com> | 2015-10-06 04:09:47 +0000 |
commit | 47818b4d6017b89e398cfbc86e3c437e0f81cfdf (patch) | |
tree | e48d6742987cb1bea9c0a86edd2f8170ad4acb6a /src | |
parent | cc3284219460351c00a153b204a561a89bcec92e (diff) |
fsp/cache_as_ram.inc and boards: Fix incorrect usage of POST_IO
POST_IO is a user-visible config bool. fsp_1_0/cache_as_ram.inc made a
mess of it, by forcing a build-time error when CONFIG_POST_IO was not
being set. fsp 1.0 boards ended 'select'ing this in their Kconfig.
Refactor fsp/cache_as_ram.inc handling of POST codes, and remove the
"select POST_IO" from boards that have it. Instead of implementing an
ad-hoc changing post code display and a delay based on port 0xed, just
encode the FSP failure code in the POST code. Since FSP failure codes
are > 16, we can encode the failure code in the lower nibble, and theirfailing function in the upper nibble.
Change-Id: Iaa3e6533e8406b16ec0689abd704984d79293952
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/8485
Tested-by: build bot (Jenkins)
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Diffstat (limited to 'src')
-rw-r--r-- | src/drivers/intel/fsp1_0/cache_as_ram.inc | 70 | ||||
-rw-r--r-- | src/mainboard/intel/bakersport_fsp/Kconfig | 1 | ||||
-rw-r--r-- | src/mainboard/intel/bayleybay_fsp/Kconfig | 1 | ||||
-rw-r--r-- | src/mainboard/intel/minnowmax/Kconfig | 4 |
4 files changed, 14 insertions, 62 deletions
diff --git a/src/drivers/intel/fsp1_0/cache_as_ram.inc b/src/drivers/intel/fsp1_0/cache_as_ram.inc index cdbda54a8b..91cfb88791 100644 --- a/src/drivers/intel/fsp1_0/cache_as_ram.inc +++ b/src/drivers/intel/fsp1_0/cache_as_ram.inc @@ -29,24 +29,14 @@ # error "CONFIG_FSP_LOC must be set." #endif -#ifndef CONFIG_POST_IO -# error "CONFIG_POST_IO must be set." -#endif - -#if CONFIG_POST_IO -# ifndef CONFIG_POST_IO_PORT -# error "CONFIG_POST_IO_PORT must be set." -# endif -#endif - #ifndef CONFIG_CPU_MICROCODE_CBFS_LOC # error "CONFIG_CPU_MICROCODE_CBFS_LOC must be set." #endif -#define LHLT_DELAY 0x50000 /* I/O delay between post codes on failure */ - cmp $0, %eax - jne bisthalt + je cache_as_ram + mov $0xa0, %eax + jmp .Lhlt cache_as_ram: post_code(0x20) @@ -61,8 +51,11 @@ find_fsp_ret: /* Save the FSP location */ mov %eax, %ebp cmp $CONFIG_FSP_LOC, %eax - jb halt1 + je find_fsp_ok + add $0xb0, %eax + jmp .Lhlt +find_fsp_ok: post_code(0x22) /* Calculate entry into FSP */ @@ -81,7 +74,11 @@ find_fsp_ret: CAR_init_done: addl $4, %esp cmp $0, %eax - jne halt2 + je car_init_ok + add $0xc0, %eax + jmp .Lhlt + +car_init_ok: /* Save FSP_INFO_HEADER location in ebx */ mov %ebp, %ebx @@ -111,50 +108,11 @@ before_romstage: movb $0xB8, %ah jmp .Lhlt -bisthalt: - movb $0xB9, %ah - jmp .Lhlt - -halt1: - /* - * Failures for postcode 0xBA - failed in find_fsp() - * - * Values are: - * 0x01 - FV signature, "_FVH" not present - * 0x02 - FFS GUID not present - * 0x03 - FSP INFO Header not found - * 0x04 - ImageBase does not equal CONFIG_FSP_LOC - Is the FSP rebased to - * a different location, or does it need to be? - * 0x05 - FSP INFO Header signature "FSPH" not found - * 0x06 - FSP Image ID is not the expected ID. - */ - movb $0xBA, %ah - jmp .Lhlt - -halt2: - /* - * Failures for postcode 0xBB - failed in the FSP: - * - * 0x00 - FSP_SUCCESS: Temp RAM was initialized successfully. - * 0x02 - FSP_INVALID_PARAMETER: Input parameters are invalid. - * 0x0E - FSP_NOT_FOUND: No valid microcode was found in the microcode region. - * 0x03 - FSP_UNSUPPORTED: The FSP calling conditions were not met. - * 0x07 - FSP_DEVICE_ERROR: Temp RAM initialization failed - * 0x14 - FSP_ALREADY_STARTED: Temp RAM initialization has been invoked - */ - movb $0xBB, %ah - .Lhlt: - xchg %al, %ah -#if CONFIG_POST_IO +#if IS_ENABLED(CONFIG_POST_IO) outb %al, $CONFIG_POST_IO_PORT -#else - post_code(POST_DEAD_CODE) #endif - movl $LHLT_DELAY, %ecx -.Lhlt_Delay: - outb %al, $0xED - loop .Lhlt_Delay + hlt jmp .Lhlt /* diff --git a/src/mainboard/intel/bakersport_fsp/Kconfig b/src/mainboard/intel/bakersport_fsp/Kconfig index 3575ab30e0..0e18423f4b 100644 --- a/src/mainboard/intel/bakersport_fsp/Kconfig +++ b/src/mainboard/intel/bakersport_fsp/Kconfig @@ -25,7 +25,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select BOARD_ROMSIZE_KB_2048 select HAVE_ACPI_TABLES select HAVE_OPTION_TABLE - select POST_IO select ENABLE_BUILTIN_COM1 if FSP_PACKAGE_DEFAULT select HAVE_FSP_BIN if FSP_PACKAGE_DEFAULT select TSC_MONOTONIC_TIMER diff --git a/src/mainboard/intel/bayleybay_fsp/Kconfig b/src/mainboard/intel/bayleybay_fsp/Kconfig index 9897cfccc4..8bf79b2ca4 100644 --- a/src/mainboard/intel/bayleybay_fsp/Kconfig +++ b/src/mainboard/intel/bayleybay_fsp/Kconfig @@ -25,7 +25,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select BOARD_ROMSIZE_KB_2048 select HAVE_ACPI_TABLES select HAVE_OPTION_TABLE - select POST_IO select ENABLE_BUILTIN_COM1 if FSP_PACKAGE_DEFAULT select HAVE_FSP_BIN if FSP_PACKAGE_DEFAULT select TSC_MONOTONIC_TIMER diff --git a/src/mainboard/intel/minnowmax/Kconfig b/src/mainboard/intel/minnowmax/Kconfig index 39f84f125f..e09efc9582 100644 --- a/src/mainboard/intel/minnowmax/Kconfig +++ b/src/mainboard/intel/minnowmax/Kconfig @@ -63,10 +63,6 @@ config VIRTUAL_ROM_SIZE depends on ENABLE_FSP_FAST_BOOT default 0x800000 -config POST_IO - bool - default n - config POST_DEVICE bool default n |