diff options
| author | Varshit B Pandya <varshit.b.pandya@intel.com> | 2022-01-17 18:27:11 +0530 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2022-01-28 15:07:51 +0000 |
| commit | 45bf0411f39d54cbee902ab58b49a771eff294f1 (patch) | |
| tree | 0ba81cdc39e2c378e2f9a4ebbe88f579a304e56d /src | |
| parent | 5f72179d572cddf7e5d202e3e2e5152fed9afbc3 (diff) | |
mb/google/dedede/var/drawcia: Change power sequencing of Camera and VCM
Drawcia's MIPI camera sensor and VCM both share the same reset GPIO
from the PCH. The current power sequence does not take this into
account, and this leads to an unbalanced ref count of the reset GPIO,
which can cause one or the other of the devices to reset unexpectedly.
This patch corrects that by explicitly sequencing the reset GPIO for
both devices, which the builtin refcounting of this driver will
automatically handle.
BUG=b:214665783
TEST=Build, boot to OS and check VCM once camera stream off
Signed-off-by: Varshit B Pandya <varshit.b.pandya@intel.com>
Change-Id: Ib676fd1f43dbd9cf75e4aff01baab4a4bb4e2a89
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61147
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Diffstat (limited to 'src')
| -rw-r--r-- | src/mainboard/google/dedede/variants/drawcia/overridetree.cb | 15 |
1 files changed, 10 insertions, 5 deletions
diff --git a/src/mainboard/google/dedede/variants/drawcia/overridetree.cb b/src/mainboard/google/dedede/variants/drawcia/overridetree.cb index cb3ff48979..2b32e9b111 100644 --- a/src/mainboard/google/dedede/variants/drawcia/overridetree.cb +++ b/src/mainboard/google/dedede/variants/drawcia/overridetree.cb @@ -314,12 +314,13 @@ chip soc/intel/jasperlake register "gpio_panel.gpio[2].gpio_num" = "GPP_D12" #reset #_ON - register "on_seq.ops_cnt" = "5" + register "on_seq.ops_cnt" = "6" register "on_seq.ops[0]" = "SEQ_OPS_CLK_ENABLE(0, 0)" register "on_seq.ops[1]" = "SEQ_OPS_GPIO_ENABLE(0, 5)" register "on_seq.ops[2]" = "SEQ_OPS_GPIO_ENABLE(1, 5)" - register "on_seq.ops[3]" = "SEQ_OPS_GPIO_DISABLE(2, 5)" - register "on_seq.ops[4]" = "SEQ_OPS_GPIO_ENABLE(2, 5)" + register "on_seq.ops[3]" = "SEQ_OPS_GPIO_ENABLE(2, 5)" + register "on_seq.ops[4]" = "SEQ_OPS_GPIO_DISABLE(2, 5)" + register "on_seq.ops[5]" = "SEQ_OPS_GPIO_ENABLE(2, 0)" #_OFF register "off_seq.ops_cnt" = "4" @@ -342,12 +343,16 @@ chip soc/intel/jasperlake register "low_power_probe" = "1" register "gpio_panel.gpio[0].gpio_num" = "GPP_D13" #power_enable_2p8 + register "gpio_panel.gpio[1].gpio_num" = "GPP_D12" #reset #_ON - register "on_seq.ops_cnt" = "1" + register "on_seq.ops_cnt" = "2" register "on_seq.ops[0]" = "SEQ_OPS_GPIO_ENABLE(0, 0)" + register "on_seq.ops[1]" = "SEQ_OPS_GPIO_ENABLE(1, 5)" #_OFF - register "off_seq.ops_cnt" = "1" + register "off_seq.ops_cnt" = "2" register "off_seq.ops[0]" = "SEQ_OPS_GPIO_DISABLE(0, 0)" + register "off_seq.ops[1]" = "SEQ_OPS_GPIO_DISABLE(1, 5)" + device i2c 0C on end end chip drivers/intel/mipi_camera |