sb/intel/bd82x6x: Drop P_LVLx support in FADT

IO MWAIT redirection is not enabled, and C-states are reported using the
_CST ACPI object, which overrides the P_LVLx values.

Change-Id: I737bd58bcda3e7c5f6591e4c2309530ff035e2c8
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55218
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>

8 files changed, 3 insertions, 23 deletions

diff --git a/src/mainboard/google/link/devicetree.cb b/src/mainboard/google/link/devicetree.cb
index 33ef305d7f..fda74da3b8 100644
--- a/src/mainboard/google/link/devicetree.cb
+++ b/src/mainboard/google/link/devicetree.cb
@@ -58,8 +58,6 @@ chip northbridge/intel/sandybridge
 			# Enable zero-based linear PCIe root port functions
 			register "pcie_port_coalesce" = "1"
 
-			register "c2_latency" = "1"
-
 			device pci 16.0 on end # Management Engine Interface 1
 			device pci 16.1 off end # Management Engine Interface 2
 			device pci 16.2 off end # Management Engine IDE-R
diff --git a/src/mainboard/google/parrot/devicetree.cb b/src/mainboard/google/parrot/devicetree.cb
index dbbb5cd906..d748277a07 100644
--- a/src/mainboard/google/parrot/devicetree.cb
+++ b/src/mainboard/google/parrot/devicetree.cb
@@ -56,8 +56,6 @@ chip northbridge/intel/sandybridge
 			# Enable zero-based linear PCIe root port functions
 			register "pcie_port_coalesce" = "1"
 
-			register "c2_latency" = "1"
-
 			device pci 16.0 on end # Management Engine Interface 1
 			device pci 16.1 off end # Management Engine Interface 2
 			device pci 16.2 off end # Management Engine IDE-R
diff --git a/src/mainboard/google/stout/devicetree.cb b/src/mainboard/google/stout/devicetree.cb
index 914ab601e0..ad700cee29 100644
--- a/src/mainboard/google/stout/devicetree.cb
+++ b/src/mainboard/google/stout/devicetree.cb
@@ -63,8 +63,6 @@ chip northbridge/intel/sandybridge
 			# Enable zero-based linear PCIe root port functions
 			register "pcie_port_coalesce" = "1"
 
-			register "c2_latency" = "1"
-
 			device pci 14.0 on end # USB 3.0 Controller
 			device pci 16.0 on end # Management Engine Interface 1
 			device pci 16.1 off end # Management Engine Interface 2
diff --git a/src/mainboard/intel/emeraldlake2/devicetree.cb b/src/mainboard/intel/emeraldlake2/devicetree.cb
index 80ae78922b..170dbaad94 100644
--- a/src/mainboard/intel/emeraldlake2/devicetree.cb
+++ b/src/mainboard/intel/emeraldlake2/devicetree.cb
@@ -45,8 +45,6 @@ chip northbridge/intel/sandybridge
 			# SuperIO range is 0x700-0x73f
 			register "gen3_dec" = "0x003c0701"
 
-			register "c2_latency" = "1"
-
 			device pci 16.0 on  end	# Management Engine Interface 1
 			device pci 16.1 off end	# Management Engine Interface 2
 			device pci 16.2 off end	# Management Engine IDE-R
diff --git a/src/mainboard/samsung/lumpy/devicetree.cb b/src/mainboard/samsung/lumpy/devicetree.cb
index 85d140c45a..716d1b85fb 100644
--- a/src/mainboard/samsung/lumpy/devicetree.cb
+++ b/src/mainboard/samsung/lumpy/devicetree.cb
@@ -56,8 +56,6 @@ chip northbridge/intel/sandybridge
 			register "gen2_dec" = "0x003c0b01"
 			register "gen3_dec" = "0x00fc1601"
 
-			register "c2_latency" = "1"
-
 			device pci 16.0 on end # Management Engine Interface 1
 			device pci 16.1 off end # Management Engine Interface 2
 			device pci 16.2 off end # Management Engine IDE-R
diff --git a/src/mainboard/samsung/stumpy/devicetree.cb b/src/mainboard/samsung/stumpy/devicetree.cb
index 6ee21af014..90ed429ec8 100644
--- a/src/mainboard/samsung/stumpy/devicetree.cb
+++ b/src/mainboard/samsung/stumpy/devicetree.cb
@@ -38,8 +38,6 @@ chip northbridge/intel/sandybridge
 
 			register "sata_port_map" = "0x3"
 
-			register "c2_latency" = "1"
-
 			register "gen1_dec" = "0x00fc1601"
 			# SuperIO range is 0x700-0x73f
 			register "gen2_dec" = "0x003c0701"
diff --git a/src/southbridge/intel/bd82x6x/chip.h b/src/southbridge/intel/bd82x6x/chip.h
index ac29944070..797c93f3aa 100644
--- a/src/southbridge/intel/bd82x6x/chip.h
+++ b/src/southbridge/intel/bd82x6x/chip.h
@@ -63,7 +63,6 @@ struct southbridge_intel_bd82x6x_config {
 	/* Override PCIe ASPM */
 	uint8_t pcie_aspm[8];
 
-	int c2_latency;
 	int docking_supported;
 
 	uint8_t pcie_hotplug_map[8];
diff --git a/src/southbridge/intel/bd82x6x/fadt.c b/src/southbridge/intel/bd82x6x/fadt.c
index b0f4777d03..77af4e89b5 100644
--- a/src/southbridge/intel/bd82x6x/fadt.c
+++ b/src/southbridge/intel/bd82x6x/fadt.c
@@ -11,7 +11,6 @@ void acpi_fill_fadt(acpi_fadt_t *fadt)
 	struct device *dev = pcidev_on_root(0x1f, 0);
 	struct southbridge_intel_bd82x6x_config *chip = dev->chip_info;
 	u16 pmbase = pci_read_config16(dev, 0x40) & 0xfffe;
-	int c2_latency;
 
 	fadt->sci_int = 0x9;
 
@@ -32,12 +31,9 @@ void acpi_fill_fadt(acpi_fadt_t *fadt)
 	fadt->pm2_cnt_len = 1;
 	fadt->pm_tmr_len = 4;
 	fadt->gpe0_blk_len = 16;
-	c2_latency = chip->c2_latency;
-	if (!c2_latency) {
-		c2_latency = 101; /* c2 unsupported */
-	}
-	fadt->p_lvl2_lat = c2_latency;
-	fadt->p_lvl3_lat = 87;
+	/* P_LVLx not used */
+	fadt->p_lvl2_lat = 101;
+	fadt->p_lvl3_lat = 1001;
 	/* P_CNT not supported */
 	fadt->duty_offset = 0;
 	fadt->duty_width = 0;
@@ -55,9 +51,6 @@ void acpi_fill_fadt(acpi_fadt_t *fadt)
 	if (chip->docking_supported) {
 		fadt->flags |= ACPI_FADT_DOCKING_SUPPORTED;
 	}
-	if (c2_latency < 100) {
-		fadt->flags |= ACPI_FADT_C2_MP_SUPPORTED;
-	}
 
 	fadt->x_pm1a_evt_blk.space_id = ACPI_ADDRESS_SPACE_IO;
 	fadt->x_pm1a_evt_blk.bit_width = 32;