diff options
| author | Raymond Chung <raymondchung@ami.corp-partner.google.com> | 2022-10-25 11:01:09 +0800 |
|---|---|---|
| committer | Werner Zeh <werner.zeh@siemens.com> | 2022-10-27 08:41:00 +0000 |
| commit | 40d3409dab132eb292eb4d46064168731c575734 (patch) | |
| tree | 1e846c4c57712866a90f7a024c842a456392c3b3 /src | |
| parent | 7ec4671f81c3a5fab33950f8635912f1a549323e (diff) | |
mb/google/brya/gaelin: Change DDR4 from interleave to non-interleave
The brask DDR4 is set to interleave, due to the limited number of
gaelin PCB layers and the traces need to be smooth,
we will use non-interleave for gaelin DDR4.
BUG=b:255399229, b:249000573
BRANCH=firmware-brya-14505.B
TEST=Build "emerge-brask coreboot" and pass MRC memory training
Change-Id: I34413343e3f7c283f49fbbdd277d9da39c09f9f8
Signed-off-by: Raymond Chung <raymondchung@ami.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68806
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Derek Huang <derekhuang@google.com>
Reviewed-by: Zhuohao Lee <zhuohao@google.com>
Diffstat (limited to 'src')
| -rw-r--r-- | src/mainboard/google/brya/variants/gaelin/Makefile.inc | 1 | ||||
| -rw-r--r-- | src/mainboard/google/brya/variants/gaelin/memory.c | 40 |
2 files changed, 41 insertions, 0 deletions
diff --git a/src/mainboard/google/brya/variants/gaelin/Makefile.inc b/src/mainboard/google/brya/variants/gaelin/Makefile.inc new file mode 100644 index 0000000000..fd45b948ff --- /dev/null +++ b/src/mainboard/google/brya/variants/gaelin/Makefile.inc @@ -0,0 +1 @@ +romstage-y += memory.c diff --git a/src/mainboard/google/brya/variants/gaelin/memory.c b/src/mainboard/google/brya/variants/gaelin/memory.c new file mode 100644 index 0000000000..98b655c100 --- /dev/null +++ b/src/mainboard/google/brya/variants/gaelin/memory.c @@ -0,0 +1,40 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <baseboard/gpio.h> +#include <baseboard/variants.h> +#include <gpio.h> +#include <soc/romstage.h> + +static const struct mb_cfg ddr4_mem_config = { + .type = MEM_TYPE_DDR4, + + .rcomp = { + /* Baseboard uses only 100ohm Rcomp resistors */ + .resistor = 100, + + /* Baseboard Rcomp target values */ + .targets = {50, 20, 25, 25, 25}, + }, + + .ect = 1, /* Early Command Training */ + + .UserBd = BOARD_TYPE_MOBILE, + + .ddr_config = { + .dq_pins_interleaved = false, + }, +}; + +const struct mb_cfg *variant_memory_params(void) +{ + return &ddr4_mem_config; +} + +void variant_get_spd_info(struct mem_spd *spd_info) +{ + spd_info->topo = MEM_TOPO_DIMM_MODULE; + spd_info->smbus[0].addr_dimm[0] = 0x50; + spd_info->smbus[0].addr_dimm[1] = 0x51; + spd_info->smbus[1].addr_dimm[0] = 0x52; + spd_info->smbus[1].addr_dimm[1] = 0x53; +} |